Fpga vhdl verilog trabalhos

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    4,098 fpga vhdl verilog trabalhos encontrados, preços em USD

    Implementar um jogo em verilog ou vhdl em vga

    $140 (Avg Bid)
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    6 ofertas

    Jogo VGA em Verilog para FPGA

    $154 (Avg Bid)
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    3 ofertas
    VHDL/verilog Encerrado left

    Segue trabalho em anexo

    $147 (Avg Bid)
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    10 ofertas
    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

    $26 (Avg Bid)
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    3 ofertas

    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    $434 (Avg Bid)
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    2 ofertas

    Olá Pedro, Você trabalho com FPGA (Zedboard) Xilinx? Preciso de um programa capaz de exibir a camera do Kinect em uma placa Zedboard.

    $100 (Avg Bid)
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    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três está...

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    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são

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    ...para formar uma palavra de 32 bits. Os sinais de controle m1, m2, m3, wPC, wMem, wRI devem ser associados às chaves de entrada. Um arquivo comprimido com todos os módulos VHDL do MIPS multiciclo é disponibilizado no Moodle. O código MIPS a ser carregado na memória está contido no arquivo mem.mif. Para exibição dos dados nos ...

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    Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do có...

    $309 (Avg Bid)
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    1 ofertas

    ...i need a simple program that can calculate time (using hight precision timer, better in micro seconds) between 2 external triggers. Here can be useed FPGA Hardware for example (personaly i prefere FPGA for such task) Frequency range from 0,1 to 100 Hz to be tested. i have programm already done (see attachement), on my laptop i got only value for frequency

    $31 (Avg Bid)
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    3 ofertas

    hey, I saw your work on the vhdl fm radio and I want to know if you're willing to send that same project.

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    1 ofertas

    The project goal is the implementation of a Verilog module to interface a high-speed ADC (250MSps) using DDR. The IO/delay shall be dynamically adjusted after reset thru a test pattern match using a test mode of the ADC. As part of the project a simulation test bench needs to be set-up to verify proper function of the interface.

    $1345 (Avg Bid)
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    This project write the Verilog to initialize and read frames from an image sensor with high quality through 8 LVDS. Requirements: Expert only for Verilog & validation simulation in Xilinx Vivado. I think you can finish this within a week if you are a Verilog expert. If you have experiences for this, please contact me sk [Removed by Freelancer

    $456 (Avg Bid)
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    I have a de1-soc fpga board ([fazer login para ver a URL]) for the detail. currently i have difficulty id generating code for image processing for my image. I have a completed matlab code that include the image and filtering kernel. I need the code to run into my fpga board.

    $35 (Avg Bid)
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    1 ofertas

    Need a vhdl project on mips pipelined processor

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    Hi olegkaravaev84, I noticed your profile and would like to offer you my SystemVerilog/Verilog FP{GA project. We can discuss any details over chat.

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    We're looking for someone with experience is sending data from an FPGA to a PC via a FT601 chip (made by FTDI) and saving the data to a binary file on the PC side.

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    an expert on FPGA and Verilog should bid only...

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    Verilog Design 3 dias left

    I have one architecture, needs the RTL verilog code for the design to be made and followed by placement and routing to derive the power.

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    1. Vivado HLS fixed code optimization 2. Introduction of parallelism and pipeling 3. c-simulation, synthesis and RTL-C cosim verification 4. IP generation in Vivado HL... Introduction of parallelism and pipeling 3. c-simulation, synthesis and RTL-C cosim verification 4. IP generation in Vivado HLS 5. Intergration of IP generated in HLS in Verilog code

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    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design

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    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.

    $166 (Avg Bid)
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    7 ofertas

    Using Altera DE1-SoC FPGA board, I want you to write a code which can do FFT of the provided signal using Quartus II and Modelsim.

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    ...(c-9896) to drew the black white picture on paper First, get the picture and manipulate it to make black and white Second, convert the picture to hex decimal and upload it to fpga ( nexys 4 ddr) using matlab Third, control the robot arm to get the pen and drew the picture. the expectation of the project is to have the following: - the required codes

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    The brightness measurement with help of PMODALS sensor ([fazer login para ver a URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([fazer login para ver a URL]) is to be used, which takes over the control. The

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    Project for Jin C. 23 horas left

    Hi Jin, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

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    Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    $200 (Avg Bid)
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    1 ofertas

    Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    $160 (Avg Bid)
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    1 ofertas

    Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant

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    This is a long term project to teach and train a software engineer about advanced Electronics, PCB design and FPGA programming. This needs between 3 and 5 hours of face to face (online video conferencing) each week and excellent communication in English. So the payments are weekly as we have the online conferecing calls. The details of what will be

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    Trophy icon Engineer consultant Business Card 4 dias left

    ...have any logo, a simple one is appreciated or also a simple standard design that represent my work is enough (google image keyword: circuit, pcb, electronic design, firmware, fpga, power electronics ) I would like to have a list of skills that I have on the business card, they are: Power Electronics, Hardware Design, Firmware, Digital Control, Altium

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    Garantido
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    382 inscrições

    I want to implement YoloV2/V3 custom object detection on FPGA. I have my trained yolo custom object detection files(.cfg and .weights) using darknet and now i want to implement yolo using this files on Xilinx FPGA. I am using ZCU102 and PYNQ evaluation boards with me.

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    FPGA IP Development Encerrado left

    I need some IPs(PHY/MAC...) for digital communication systems.

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    I Need Programmer Encerrado left

    I Need Programmer For FPGA Board & Software Development.

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    build mac unit Encerrado left

    build mac unit using verilog language. I have already done the multypler part and I need help to build the rest

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    1- I need someone to design a fully-digital, hardware-based keyboard encoder for a 16-key (4×4) matrix keyboard. 2- The design is to be implemented using an FPGA and verified by both simulation and physical implementation using a development board. 3- You should have Development boards, design software and encoder hardware 4- Separate documents will

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    Basically I would like to have the verilog coding to build on my basys3 hardware. required to control the LED with left and right pushbutton within a range, to code different frequency for the LED within that range, to code one letter on each 7segment and the speed of the letter being displayed is depend on the frequency coded to the led. to code a

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    ...explaining different aspects of that algorithm. - Explain FPGA developers about Blockchain, cryptocurrency, how crypto-mining works. How to mine that particular algorithm. - Work with them and help them understand how crypto-mining works. And how to mine that perticular algorithm. - Support FPGA developers throughout development. - Must be fluent in

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    FPGA mining hardware - Xiling FPGA - Nexys Video - Can be leveraged from open source bitcoin miner code. - Based on Verilog. - Provide source code, constraints and full recipe for synthesis, implementation and bitstream generation - Connectivity via JTAG to the host (via USB). May consider UART instead, but as a less desirable solution. Mining software:

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    I have a VHDL source for the Altera EP3C25F256C8 FPGA design. I like an expert to setup the timing and fitting parameters to give the design optimum performance. I use Quartus II software version 8.1

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    7 ofertas

    ...distance measurement with help of MB1010 ultrasonic distance sensor ( [fazer login para ver a URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core ([fazer login para ver a URL]) is to be used, which takes over the control

    $272 (Avg Bid)
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    2 ofertas

    Your first task is create an EAGLE 7.x library (a symbol and a footprint) for the part (ORT42G5-3BM484C) for it. Part info: Please refer to the attached datasheet file. YOU MUST PROVIDE complete EAGLE 7.x library file. Second task is create an EAGLE 7.x schematic for a breakout board. You can refer the evaluation board schematic. Evaluation board schematic: Please refer to the attached schematic ...

    $250 - $750
    Secreto
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    Details are included in the preliminary document. In short, we would lik...separate bids. I may even be posting them as time and material. NOTE: The intention is to eventually take this to a custom SOC implementation with the "link sharing" portion being FPGA programmed in and the rest (SPROC(s) in the doc) running on an ARM with a mcro linux kernel.

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    ADC
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    FPGA project Encerrado left

    Looking for someone how has knowledge in FPGA programming hardware and software.

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    FPGA verilog Encerrado left

    Using ModelSim or Quartus II for solving some problems i am working on

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    Project for Loi L. Encerrado left

    Hi Loi L., I noticed your previous work on the FIFO implementation of a FM Radio in VHDL. I was wondering if you would like to work on that same project. We can discuss any details over chat.

    $150 (Avg Bid)
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    1 ofertas