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    3,067 fpga trabalhos encontrados, preços em USD

    A presença de erros em dados digitais é um problema frequente em sistemas computacionais que lidam com transmissão e armazenamento de informação. Em alguns contextos, como o de computação aproximada, admite-se uma taxa ainda maior de erros para alcançar uma redução no consumo de energia. Nesses casos, torna-se imprescindível o controle de erros. Isto pode ser feito através do uso d...através do uso de códigos detectores (e corretores) de erros, que são capazes de detectar (e corrigir) a informação corrompida através de redundância inserida nos dados. Nesse projeto, o objetivo é gerar um codificador baseado em paridade e um detector de erros que avisa qu...

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    O freelancer deverá conhecer as linguagens = C / vhdl / verilog e já ter trabalhado com FPGA / ASIC Portar e otimizar um código que já tenho pronto em "c" para vhdl ou verilog esse código gera uma string de 14 / 15 dígitos, será usado uma placa fpga xillinx spartan 6 ( a empresa xillinx disponibiliza todo o ambiente necessário ). converter a string em Sha256 usando placa asic depois de convertido em sha256 compara com um sha256 informado no inicio do processo, se igual finaliza, se não reinicia o processo. Deverá ser usado a Raspberry Pi 3 para termos uma interface ( teclado e monitor ) para inserir o código inicial

    $225 (Avg Bid)
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    2 ofertas

    Implementar um jogo em verilog ou vhdl em vga

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    6 ofertas

    Jogo VGA em Verilog para FPGA

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    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

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    Olá Pedro, Você trabalho com FPGA (Zedboard) Xilinx? Preciso de um programa capaz de exibir a camera do Kinect em uma placa Zedboard.

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    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são usados para controlar LEDs que utilizem drives LPD6803, WS2801, etc. O software envia os dados (frames) através de pacote UDP para o hardware (FPGA) que recebe, armazena em buffer de memoria RAM do FPGA e então envia estes dados para os LEDs através de uma porta SPI que deve ser implementada dentro do FPGA. Monitorando e capturando os pacotes UDP que o computador...

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    I want to create programming routines to be recorded on an FPGA

    $33 / hr (Avg Bid)
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    Project to be done in VHDL, so I am looking for an expert. The objective is to create a testbench for one circuit, and simulate the a few operations including storing data in it as well as retrieving data from it. I can share more details in PM.

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    Project to be done in VHDL, so I am looking for an expert. The objective is to create a testbench for one circuit, and simulate the a few operations including storing data in it as well as retrieving data from it. I can share more details in PM.

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    I am looking to hire an individual who really understand this subject. should be able to solve any problems related to this subject. communicate and be able to write good programming and simulation designs.

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    Hi Mohammed Ibrahim, I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    Hi Mohammed Ibrahim, I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    1 ofertas

    I want to use accelerometer sensor on FPGA, in order to do that I need I2C protocol implementation in VHDL so I can continue my work on the project. I want the module to get the address of the sensor + bit for R/W , and the internal register address of the sensor, and get the data by reading, or write to the register.

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    FPGA, Quartus , VHDL 2 dias left
    VERIFICADO

    Using the fixed point arithmetic measure current according to the following circuit

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    The main objective of the digital clock is to display the time digitally using 7-segment display on Artix-7 FPGA Board. The digital clock by default displays the run time and time can be set by using time set assigned to switch on board. The digital clock designed is a 24-clock hour format. It displays the time in format of hours:minutes: seconds.

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    I need to design gradient descent optimizer on FPGA in verilog language and code should be synthesizable. entire design should be pipelined. Input and outputs should be in single precision floating point representation. loss or cost function is mean square error loss for 2D variables, minimise the above cost functions to achieve the optimised value. I have developed gradient descent optImizer on python , below attached file is code of it. I want same implementation in verilog

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    Good knowledge of VHDL is required. Libero Soc and Microsemi will be used The simulator will be Aldec Active-HDL, linting with Aldec Alint Design of a basic control board, standard interfaces, no high speed interfaces, no transceivers. DO-254 DAL C, basic knowledge is a plus some math algorithm in fixed point will be implemented on the hardware for motor control Supervision of our expert designers, short daily meeting and 1h weekly with reports on activities and scheduling contract will be extended month by month (we have budget for 6 months).

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    1- Signal processing using ML on a computer (C Language) 2- using Single and dual ARM (C Language) 3-using FPGA Zedboard programmable logic (VHDL Language)

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    We need due to the large quantity of deployment, no full commitment of supplier, and because we are in the need of operating in multi-channel our own SDR PCB. Currently there are Low-Cost + High Quality SDR's that have one FPGA and one Transceiver. The Software Defined Radio must have its own PCB. It need to operate on both GSM, EDGE, 4G LTE, 5G simultaneously using one FPGA. We understand it would need 4 transceivers, with each one TX + one RX and on-board a strong amplifier. The power though the board for long-range connectivity via the TX + RX amplifiers need to be 15W+. The BOM should be similar to the X115 - however this operating on only one channel within the cellular spectrum. We would need 4 channels: 4 x LTE or mix of GSM, EDGE, 4G LTE, 5G. We would need so...

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    FPGA in Distributed optical fiber sensor

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    Its related (ML and DL, also About hardware accelerators such as GPU and FPGA-SoC ) i have review paper it around 70% need to (add more information and details, reduce the number of pages ) actually the paper reached to 60 page until now it need to be 30 pages m looking to give you the paper and you give to me ready for publication. Must be BRITISH ENGLISH

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    Verilog FPGA programming in Linux

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    ...require good fpga or asic design experience. Along with pcb design and assembly. The first product we wish to create will be a video splitter. The principle is simple - we just need to take a 2160p (4k) hdmi video input and divide it into x4 1080p (hd) hdmi outputs in a 2x2 tiled arrangement. At up to 60 hz 4:4:4. Another product which we would like to design may be a little more complicated, as this one has multiple device synchronisation requirements, so some memory and buffering of video frames will be required. The third product would require a tight integration with one of our existing products. In this product we use an nvidia jetson orin module on an off the shelf carrier board. We would like to transfer video frames direct from the gpu over the pci express bus to an ...

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    I am working on the project of a "Portable Ultrasound Sensor". I would basically want the redesign the specific paper (for more information ask me for the paper). At the moment, I am debugging the serial LVDS capture code from my Analog-Front_end (AFE5832LP) to FPGA (Zynq Ultrascale_plus MPSoC). Is there any possibility for you to help me in this regard?

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    I have put below the specifications of the Static Var Generator device that the PCBs go together to create. ●Rapid dynamic real-time compensation ● High precision reactive compensation, PF>0.99 ● Reactive compensation range: -1~1(adjustable) ● No overcompensation, under-compensation, resonance, capacity fading ● DSP+FPGA, high-speed operational capability ● Response time<10ms ● Protection: overvoltage, overcurrent, overtemperature ● Communication: Ethernet, RS485 ● Low noise: intelligent variable-speed cooling fan ● Germany brand IGBT chip ● Texas Instrument DSP chip, high speed, and reliable performance ● Modular design, customized modules in parallel Rated Voltage(V) 120V/220V/400V/480V/690V Rated Frequency (Hz) 50HZ/60HZ Network Configuration...

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    I have put below the specifications of the Static Var Generator device that the PCBs go together to create. ●Rapid dynamic real-time compensation ● High precision reactive compensation, PF>0.99 ● Reactive compensation range: -1~1(adjustable) ● No overcompensation, under-compensation, resonance, capacity fading ● DSP+FPGA, high-speed operational capability ● Response time<10ms ● Protection: overvoltage, overcurrent, overtemperature ● Communication: Ethernet, RS485 ● Low noise: intelligent variable-speed cooling fan ● Germany brand IGBT chip ● Texas Instrument DSP chip, high speed, and reliable performance ● Modular design, customized modules in parallel Rated Voltage(V) 120V/220V/400V/480V/690V Rated Frequency (Hz) 50HZ/60HZ Network Configuration...

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    Introdouction Making a wave music player by storing the wave audio data in a mif file to get the audio data in to the memory and can use FSM control for play,pause,rewind etc functions.

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    CIS_reader Encerrado left

    Need to program an ICE40 FPGA in order to interface the CIS front end

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    This project is for the pcb design, I will share the schematics in a pdf also it has an fpga that probably needs programmed.

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    This project is for the pcb design, I will share the schematics in a pdf also it has an fpga that probably needs programmed.

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    Make the RED square move and if its hits any of the sides, then the player loses the game. Add a graphic indicating the player lost. Add a points keeping system on the screen or FPGA

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    verilog coding game Encerrado left

    Make the RED square move and if its hits any of the sides, then the player loses the game. Add a graphic indicating the player lost. Add a points keeping system on the screen or FPGA

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    VHDL and FPGA Expert Encerrado left

    Need a VHDL and FPGA Systems expert 1. To create a modular system using VHDL. 2. To use simulation and test to verify the correctness of the design. 3. To demonstrate the milestones working on a target FPGA device. 4. To document the entire design process - recording the technical detail and justification of the work done. Detailed document will be provided on chat

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    Accelerate a python code and Convert to Python Overlay on Zynq FPGA development board with VIVADO HLS. MUst be good in PYNQ and VIVADO HLS

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    I am looking someone having experience with MIPI CSI-2 TX (FPGA to other device, not the MIPI-CSI2 Camera into FPGA) on Xilinx MPSoC Platform and Petalinux. Its a consultation and/or development project. Anyone having experience with MIPI-CSI2 TX with any embedded Linux (ARM or other embedded platforms) can also contact me here at Project. It is moreover embedded Linux driver development work based on MPSoC FPGA.

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    Ultrasound sensor Encerrado left

    Hi, I am working on the making prototype of an ultrasound sensor. The project includes three evaluation boards to capture ultrasound data from the body through the computer. This project includes the transmitter, analog front end, and FPGA board. I need someone who is a professional in FPGA engineering who could help me and supervise me.

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    I keep receiving errors in trying to communicate my fpga with my arduino via spi

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    What i need to be done is a FPGA for BladeRF or LimeSDR, The FPGA Should LIsen on frequency For a signal with the RX BladeRF or LimeSDR Annetna and once a signal is detected on that frequency the TX Anntena should trasmit a signal and then stop

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    Accelerate python code using Vivado HLS on PYNQ FPGA

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    Implementar, simular FFT en entorno aldec , bajo la plataforma Atlys Spartan-6. Simular e implementar FFT en dicha plataforma, desarrollar código VHDL y detallar minuciosamente paso a paso, tomar captures y realizar documento de word detallando cada paso la oferta es de 90 usdt. Se cuenta con la tarjeta en físico por lo cual se ofrece conexión remota

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    We have a zedboard code which takes data from external adc and transfer over ethernet to pc. Everything is working fine. After data acquisition, we are transferring data of around 75k samples of 16 bit each to PC. Its taking around 3 min for transfer. Need work on data transfer rate and improve the same.

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    FPGA xilinks Encerrado left

    Needed specialist for modify and compile cores for xilinks FPGA ,

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    VHDL designer -- 2 Encerrado left

    ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform

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    VHDL designer Encerrado left

    ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform

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    Need to convert MATLAB code to synthesizable VHDL code. I am using DE2 FPGA board for testing

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    I need a bitstream and a Linux-adapted mining software for my JungleCat with VU35P from Xillien. Freelancer will provide Bitstream and I will test its hash rate and stability. A board can also be provided for testing. Also, I need long-term support. Also write the word VCU at the end of the offer.

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    Need to Convert MATLAB code to VHDL code. I Have a MATLAB code i want someone who can convert that code to a sytnthesizable VHDL code for ALtera FPGA.

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    I will love to chat with you about my project. Please let me know when you can https://www.freelancer.com/projects/verilog-vhdl/FPGA-expert-34634495/details

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    Artigos da Comunidade dos Principais fpga