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    6,158 latest vhdl verilog trabalhos encontrados, preços em USD

    Implementar um jogo em verilog ou vhdl em vga

    $140 (Avg Bid)
    $140 Média
    6 ofertas

    Jogo VGA em Verilog para FPGA

    $154 (Avg Bid)
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    3 ofertas
    VHDL/verilog Encerrado left

    Segue trabalho em anexo

    $147 (Avg Bid)
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    10 ofertas
    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

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    3 ofertas

    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    $434 (Avg Bid)
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    2 ofertas
    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três está...

    $472 (Avg Bid)
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    3 ofertas

    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são

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    ...para formar uma palavra de 32 bits. Os sinais de controle m1, m2, m3, wPC, wMem, wRI devem ser associados às chaves de entrada. Um arquivo comprimido com todos os módulos VHDL do MIPS multiciclo é disponibilizado no Moodle. O código MIPS a ser carregado na memória está contido no arquivo mem.mif. Para exibição dos dados nos ...

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    Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do có...

    $309 (Avg Bid)
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    1 ofertas

    I'm a techie. I'm making a web page with blogs on technology and life style. In this context, I'm looking for rockstar blog writers who can get me most possible views with their quality non-duplicate content. Its just beginning, if this clicks i have series of Ideas to implement and if I like the work and quality I may have continuous business with THE ROCKSTARS.

    $17 (Avg Bid)
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    ...clicking on "comments" for the post comment box to open as well. 6. able to re-post comments 7. fixing the image block to accept gif 8. (this is the most important one) for the latest comments to be shown, not the first ones. 9. repost button. 10. Heart post to be moved to the top. 11. Posting timestamp 12. Be able to see your comment once it has been posted

    $80 (Avg Bid)
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    Hello there, I have an eCommerce website built several years ago and I would like to upgrade from Magento ver. 1.4.2.0 to 1.9 or latest. Thank you.

    $670 (Avg Bid)
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    75 ofertas

    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results

    $140 (Avg Bid)
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    1 ofertas

    Need word, sentence, grammer changes on pdf with latest version of INDESIGN Would also like to create along term relationship for on going creative graphic work (not programming) in building a membership website, with online training. I have original source files

    $16 (Avg Bid)
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    12 ofertas

    I have an ios VOIP app customized using Linphone source code. I need to upgrade using the latest Linphone version. I want to keep existing rules and customization but modify the audio options and turn on a few more options. My app name is VoiceHi which can be downloaded from apple store . Please see attached file. Please use the logo, app icon and

    $150 (Avg Bid)
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    Upgrading Linphone To Latest 4 dias left
    VERIFICADO

    I have an ios VOIP app customized using Linphone source code. I need to upgrade using the latest Linphone version. I want to keep existing rules and customization but modify the audio options and turn on a few more options. My app name is VoiceHi which can be downloaded from apple store and google play. Please see attached file.

    $235 (Avg Bid)
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    8 ofertas

    I want to publish a book about latest technologies intended for CEO/CIO/Solution Architects/Enterprise Architects. The book will have about ten chapters each having 10-12 pages. The research will be needed as well. I already have some material written, which will need strengthening with additional research. Contact me for details.

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    ADC
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    VHDL implemented in altera de2 board

    $430 (Avg Bid)
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    4 ofertas

    update a simple CS CART website version from 4.6 to 4.9 (latest) -->It is one of the default templates used in frontend

    $167 (Avg Bid)
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    3 ofertas

    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

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    A very simple processor is designed, need to write vhdl codes(few components already written) for it and implement the microprogrammed Control unit.

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    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

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    Verilog simulation of two action-reaction processes

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    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

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    7 ofertas
    $10 Média
    1 ofertas

    Vhdl is needed

    $27 (Avg Bid)
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    1. I will create a new Aliyun server 2. Create new Magento 2 3. Transfer current Magento 1 all data to Magento 2 4. Current server is hosting on Siteground with Magento 1

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    we have clipshare 4.0. And we already customized a lot. the current site is not mobile friendly. we purchased the latest version of clipshare, we just need you to integrate the latest template with our current template, so it's mobile friendly. Need to have smarty template experience. clipshare demo [login to view URL] the interface change

    $6949 (Avg Bid)
    Destacado
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    ...company in the US. Site has been using Joomla 2.5 with tour(custom activity booking module)and some modules. Need merge,migrate and recreate a site. We are discuss to upgrade latest Joomla version but, wordpress has more capability, extension and integrations, decide to migrate and integrate to wordpress. >>>>>>>>>>>>>>>>>>>>&...

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    How does the parking system work? The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type...

    $766 (Avg Bid)
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    3 ofertas

    Need help program FPGA with Artix-7 using Verliog.

    $125 (Avg Bid)
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    5 ofertas
    $20 / hr Média
    3 ofertas

    I would like a VHDL code that reads 3 txt file and produces 3 txt file. The inputs text files produced by Matlab in binary. please see the attachment for the code I attempted to do but it not working, and text​ input files.

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    ...with 32 bit instructions and 16 bit data, to be implemented using VHDL. In case of any doubts kindly contact to clarify requirements before making offers. Expectations: - seeking sincere and diligent freelancers. - good understanding and practical experience with digital design using VHDL. - use of Vivado Design Suite (Webpack 2017.4) - aligned and meaningfully

    $297 (Avg Bid)
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    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

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    1 ofertas

    Implement the Zen Protocol in the FPGA and update the Mining App

    $1220 (Avg Bid)
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    ...but you also have to write the result to the $rd register as R-type instructions require. Write a structural Verilog on Altera Quartus II tool to implement a 32-bit R-type MIPS. Only structural Verilog is allowed, dataflow and behavioral Verilog is not allowed except for the register module. This means you cannot use assign, ifelse, always, ?: and etc

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    using VHDL: It’s a simple game of ping pong but only one line using the LED lights. the light will go backward and forward, the player needs to click on control at the edge of last two LED to flip the direction of the LED lights, it will start slow and it will speed up as you play, and the seven segment display will display how many time you hit the

    $14 / hr (Avg Bid)
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    questions on Hardware Design Language and Programmable Logic Regarding Verilog or System Verilog questions. - Writing a function / typdef struct /identifing the types of errors, ... - (pulse width modulation, frequency dividers, counters, sorting, generating a sequence like a Fibonacci sequence, finite state machine, test benches, math functions

    $25 (Avg Bid)
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    Make a serial interface system using Verilog

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    Proyecto enfocado al diseño VHDL sobre FPGAS. Desarrollo de código y de bancos de pruebas, verificación del funcionamiento y resolución de algunas cuestiones. Tiene que estar terminado para el día 17 de diciembre. Se adjunta toda la descripción de lo que hay que hacer, así como unas plantillas para las soluciones y algunos bancos de pruebas...

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    Use a Verilog and Do exactly what is on the paper and hand me a report with codes, synthesized diagrams, and a description comparing the different state assignments

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    VHDL questions Encerrado left

    I have some VHDL questions which I nedd to be solved .

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    Its a small assignment. If you are an expert and have worked on it before. text me

    $129 (Avg Bid)
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    9 ofertas

    ...but you also have to write the result to the $rd register as R-type instructions require. Write a structural Verilog on Altera Quartus II tool to implement a 32-bit R-type MIPS. Only structural Verilog is allowed, dataflow and behavioral Verilog is not allowed except for the register module. This means you cannot use assign, ifelse, always, ?: and etc

    $28 (Avg Bid)
    $28 Média
    5 ofertas

    ...minimum resource filter bank in VHDL in the simplest possible way. It can be done on HDL designer or Simulink VIVADO Signal Generator. * Create a word file with short explanations how VHDL model works and add guidelines what algorithm was used to implement DFT. * Do a bit-true simulation in order to confirm that VHDL model works the same as the Simulink

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    9 ofertas
    PLL in VHDL Encerrado left

    Add in our Design a PLL for variable clock speed

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    12 ofertas

    Need to update a wordpress site to the latest version. I have created a dev site which is a copy of the live site - where you should test the upgrade first. It's should be a fairly simple upgrade, although when I tried to upgrade last time it has a critical error during the upgrade and I had to restore it

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    24 ofertas