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    2,768 part time freelance vhdl verilog trabalhos encontrados, preços em USD

    Implementar um jogo em verilog ou vhdl em vga

    $140 (Avg Bid)
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    6 ofertas

    Jogo VGA em Verilog para FPGA

    $154 (Avg Bid)
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    3 ofertas
    VHDL/verilog Encerrado left

    Segue trabalho em anexo

    $147 (Avg Bid)
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    10 ofertas
    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

    $26 (Avg Bid)
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    3 ofertas

    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    $434 (Avg Bid)
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    2 ofertas
    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três está...

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    3 ofertas

    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são

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    ...para formar uma palavra de 32 bits. Os sinais de controle m1, m2, m3, wPC, wMem, wRI devem ser associados às chaves de entrada. Um arquivo comprimido com todos os módulos VHDL do MIPS multiciclo é disponibilizado no Moodle. O código MIPS a ser carregado na memória está contido no arquivo mem.mif. Para exibição dos dados nos ...

    $96 (Avg Bid)
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    3 ofertas

    Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do có...

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    1 ofertas

    Snake Game : 1.) Should run on Altera DE2 Board or on basy3 . 2.) Should Support VGA. 3.)Needed in a 3 days. skills:- verilog software:vivado i need this project in verilog and not in VHDL

    $78 (Avg Bid)
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    5 ofertas
    Task on verilog 3 bit ALU 5 dias left
    VERIFICADO

    Task on verilog 3 bit ALU Deadline 1 day Amount USD 40

    $43 (Avg Bid)
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    14 ofertas

    Need a small task on 3 bit ALU using verilog. Deadline 18 hours amount usd 30 .

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    3 ofertas

    I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data

    $127 (Avg Bid)
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    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

    $16 / hr (Avg Bid)
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    28 ofertas

    I have project ready already just need some help!

    $194 (Avg Bid)
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    9 ofertas
    SRAM FPGA controller in Verilog Encerramento left
    VERIFICADO

    Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix it.

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    6 ofertas

    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

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    3 ofertas

    risc processor design and test, more detail I will provide on chat

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    16 ofertas

    Create a custom SPI master controller with single, dual, and QUAD operation modes in VHDL for a MAX V CPLD.

    $391 (Avg Bid)
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    9 ofertas

    we need a technical content writer who knows the system Verilog, OVM and UVM.

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    7 ofertas

    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

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    We are looking for C++ programmer with experience in building GUI using QT. Preferable EDA/ Verilog Experience with background in Electrical Engineering

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    15 ofertas

    Please refer the attached document. This is the base paper of my p...of my project. I want to do my project on 64 bit square root carry select adder. I request you to help me with the coding in Verilog using Xilinx in gate level or switch level modelling. Can you please share the cost and the time line for the code. I will need it as soon as possible.

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    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

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    12 ofertas

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $149 (Avg Bid)
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    4 ofertas

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like ...Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

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    Vhdl LCD finctional Encerrado left

    In ready projekt on vhdl (tic tac toe game) I need to add state od the gamę on LCD [login to view URL]

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    5 ofertas
    DSP48E1 help Encerrado left

    Hi! I need some help with DSP48E1 verilog instantiation.

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    I need to write a VHDL code for transfer data from 2 zedboard using ethernet without using a zynq-processor

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    I want clients Encerrado left

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

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    I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.

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    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

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    add memory protection into the operating system, This project needs both hardware and software knowledge, you will be creating / implementing OS functions on the PicoBla...hardware and software knowledge, you will be creating / implementing OS functions on the PicoBlaze, programming in assembler. You may also need to modify the hardware using VHDL.

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    Hello guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image table in the files section. Thank you a lot...

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    Hello guys I...cache memory). I would comments on the code and the resulting image as deliverables. 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works. Again comments on the code please. P.S.: 8 by 8 vhdl integer divider I attach the image table in the files section. Thank you a lot for your bidding :)

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    écrire un code vhdl , pour DE0 nano , permettant de lire la température a partir d'une entrée analogique avec un LM19 et en sortie il faut emmètre des son avec un buzzer ( différent fréquence en fonction de la température )

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    Hello guys I will ...language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory) 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works I attach the image table in the files section. Thank you a lot for your bidding :)

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    3 ofertas

    I need help with the structural in Xilinx. I will give you full details. Regards

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    ...am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

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    Hi, my name is Paride, nice to meet you. i have got your conctact from Alessandro, a classmate. I am working on a easy Vhdl project, i already wrote all the code, the simolulation is working, but i need your help for two fast tasks: • I need to assign the pins on my FPGA, i can't find the correct pin of 2 serial signals. • i need you to check if the

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    verilog project Encerrado left

    verilog coding using putty or terminal. if you are interested i will give more information.

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    System verilog Encerrado left

    I want help with system Verilog coding. I have a working code that I want revised a bit.

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    8 ofertas
    ADC - VHDL Implement Encerrado left

    Implement an AD2949 IC input block and some more

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    11 ofertas
    verilog project Encerrado left

    mtech Verilog project

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    looking for someone who can convert Open CL algorithm into FPGA Verilog project

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    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

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    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

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    I want a content writer who knows digital design or digital electronics and vhdl subjects very well.

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    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

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    2 ofertas

    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    $20 / hr (Avg Bid)
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    9 ofertas