Sonet vhdl verilog jobs

Filtro

Minhas pesquisas recentes
Filtrar por:
Orçamento
para
para
para
Tipo
Habilidades
Idiomas
    Estado do Trabalho
    2,779 sonet vhdl verilog trabalhos encontrados, preços em USD

    Implementar um jogo em verilog ou vhdl em vga

    $140 (Avg Bid)
    $140 Média
    6 ofertas

    Jogo VGA em Verilog para FPGA

    $154 (Avg Bid)
    $154 Média
    3 ofertas

    Segue trabalho em anexo

    $147 (Avg Bid)
    $147 Média
    10 ofertas

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

    $26 (Avg Bid)
    $26 Média
    3 ofertas

    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    $434 (Avg Bid)
    $434 Média
    2 ofertas

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três está...

    $472 (Avg Bid)
    $472 Média
    3 ofertas

    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são

    $2065 (Avg Bid)
    $2065 Média
    2 ofertas

    ...para formar uma palavra de 32 bits. Os sinais de controle m1, m2, m3, wPC, wMem, wRI devem ser associados às chaves de entrada. Um arquivo comprimido com todos os módulos VHDL do MIPS multiciclo é disponibilizado no Moodle. O código MIPS a ser carregado na memória está contido no arquivo mem.mif. Para exibição dos dados nos ...

    $96 (Avg Bid)
    $96 Média
    3 ofertas

    Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do có...

    $309 (Avg Bid)
    $309 Média
    1 ofertas

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $182 (Avg Bid)
    $182 Média
    9 ofertas

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $146 (Avg Bid)
    $146 Média
    2 ofertas

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like ...Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    $415 (Avg Bid)
    $415 Média
    2 ofertas

    In ready projekt on vhdl (tic tac toe game) I need to add state od the gamę on LCD [login to view URL]

    $32 (Avg Bid)
    $32 Média
    5 ofertas

    Hi! I need some help with DSP48E1 verilog instantiation.

    $4 / hr (Avg Bid)
    $4 / hr Média
    5 ofertas

    I need to write a VHDL code for transfer data from 2 zedboard using ethernet without using a zynq-processor

    $208 (Avg Bid)
    $208 Média
    12 ofertas

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

    $18 (Avg Bid)
    $18 Média
    2 ofertas

    I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.

    $19 / hr (Avg Bid)
    $19 / hr Média
    11 ofertas

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    $154 (Avg Bid)
    $154 Média
    7 ofertas

    add memory protection into the operating system, This project needs both hardware and software knowledge, you will be creating / implementing OS functions on the PicoBla...hardware and software knowledge, you will be creating / implementing OS functions on the PicoBlaze, programming in assembler. You may also need to modify the hardware using VHDL.

    $499 (Avg Bid)
    $499 Média
    11 ofertas

    Hello guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image table in the files section. Thank you a lot...

    $111 (Avg Bid)
    $111 Média
    1 ofertas

    Hello guys I...cache memory). I would comments on the code and the resulting image as deliverables. 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works. Again comments on the code please. P.S.: 8 by 8 vhdl integer divider I attach the image table in the files section. Thank you a lot for your bidding :)

    $25 (Avg Bid)
    $25 Média
    3 ofertas

    écrire un code vhdl , pour DE0 nano , permettant de lire la température a partir d'une entrée analogique avec un LM19 et en sortie il faut emmètre des son avec un buzzer ( différent fréquence en fonction de la température )

    $36 (Avg Bid)
    $36 Média
    2 ofertas

    Hello guys I will ...language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory) 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works I attach the image table in the files section. Thank you a lot for your bidding :)

    $28 (Avg Bid)
    $28 Média
    3 ofertas

    I need help with the structural in Xilinx. I will give you full details. Regards

    $24 (Avg Bid)
    $24 Média
    24 ofertas

    ...am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

    $38 (Avg Bid)
    $38 Média
    112 ofertas

    Hi, my name is Paride, nice to meet you. i have got your conctact from Alessandro, a classmate. I am working on a easy Vhdl project, i already wrote all the code, the simolulation is working, but i need your help for two fast tasks: • I need to assign the pins on my FPGA, i can't find the correct pin of 2 serial signals. • i need you to check if the

    $58 (Avg Bid)
    $58 Média
    1 ofertas

    verilog coding using putty or terminal. if you are interested i will give more information.

    $135 (Avg Bid)
    $135 Média
    27 ofertas

    I want help with system Verilog coding. I have a working code that I want revised a bit.

    $104 (Avg Bid)
    $104 Média
    9 ofertas

    Implement an AD2949 IC input block and some more

    $532 (Avg Bid)
    $532 Média
    12 ofertas

    mtech Verilog project

    $21 (Avg Bid)
    $21 Média
    19 ofertas

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    $180 (Avg Bid)
    $180 Média
    7 ofertas

    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

    $2830 (Avg Bid)
    $2830 Média
    15 ofertas

    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

    $108 (Avg Bid)
    $108 Média
    12 ofertas

    I want a content writer who knows digital design or digital electronics and vhdl subjects very well.

    $83 (Avg Bid)
    $83 Média
    21 ofertas

    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

    $101 (Avg Bid)
    $101 Média
    2 ofertas

    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    $20 / hr (Avg Bid)
    $20 / hr Média
    9 ofertas

    Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am

    $131 (Avg Bid)
    $131 Média
    12 ofertas

    Hi there! I'm based in Ahmedabad, India. This project is related to lightweight cipher, cryptography. I have attached a pdf containing information relevant to this project w...design so that I can perform power analysis on it. Need the code properly working in two days. I looking for a Clock based implementation on existing design Language used : VHDL

    $55 (Avg Bid)
    $55 Média
    4 ofertas

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found...clock based design so that I can perform power analysis on it. Need the code properly working in two days. Note: Clock based implementation on existing design Language used : VHDL

    $30 (Avg Bid)
    $30 Média
    2 ofertas

    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

    $4436 (Avg Bid)
    $4436 Média
    27 ofertas

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    $390 (Avg Bid)
    $390 Média
    3 ofertas

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be ...individual modules are successfully executing but the final result doesn't appear which you can help me in debugging the same ) Note: Problem in debugging the code Language used : VHDL

    $158 (Avg Bid)
    $158 Média
    9 ofertas

    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

    $65 (Avg Bid)
    $65 Média
    18 ofertas

    expert on VHDL is need for a project on digital thermostat. This is a simple task. expert only should bid

    $73 (Avg Bid)
    $73 Média
    20 ofertas

    build a communication block in VHDL at Xilinx environment

    $402 (Avg Bid)
    $402 Média
    14 ofertas

    Implement Communication VHDL Comm port on Xilinx FPGA part

    $126 (Avg Bid)
    $126 Média
    16 ofertas

    i have a task related to Communication VHDL Xilinx, i will share the details in chat.

    $115 (Avg Bid)
    $115 Média
    19 ofertas

    FPGA TCPIP implementation using Verilog

    $21 / hr (Avg Bid)
    $21 / hr Média
    16 ofertas
    $23 Média
    18 ofertas