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    2,826 sonet vhdl verilog trabalhos encontrados, preços em USD

    Implementar um jogo em verilog ou vhdl em vga

    $140 (Avg Bid)
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    6 ofertas

    Jogo VGA em Verilog para FPGA

    $154 (Avg Bid)
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    3 ofertas
    VHDL/verilog Encerrado left

    Segue trabalho em anexo

    $147 (Avg Bid)
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    10 ofertas
    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

    $26 (Avg Bid)
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    3 ofertas

    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    $434 (Avg Bid)
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    2 ofertas
    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três está...

    $472 (Avg Bid)
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    3 ofertas

    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são

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    ...para formar uma palavra de 32 bits. Os sinais de controle m1, m2, m3, wPC, wMem, wRI devem ser associados às chaves de entrada. Um arquivo comprimido com todos os módulos VHDL do MIPS multiciclo é disponibilizado no Moodle. O código MIPS a ser carregado na memória está contido no arquivo mem.mif. Para exibição dos dados nos ...

    $96 (Avg Bid)
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    3 ofertas

    Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do có...

    $309 (Avg Bid)
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    1 ofertas

    The project is described in the uploaded file, however one can alter the project as long as keeping the equipments and the goal of the project intact

    $155 (Avg Bid)
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    1 ofertas

    Complete a design that includes most of the elements to be used in the CPU

    $138 (Avg Bid)
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    7 ofertas

    Hello i have a code of piano synthesizer using VHDL (vivado) and i want to understand it and fix it ... can you help me ?

    $12 / hr (Avg Bid)
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    1 ofertas
    Verilog code 5 dias left

    Please do what is in the paper and hand me the code, testing waveforms and synthesized diagrams

    $102 (Avg Bid)
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    5 ofertas

    ...ability to extract and critically evaluate data for an unfamiliar digital design problem.‎ • The application of appropriate design methods to the VHDL design.‎ • The selection appropriate analysis tools, VHDL model abstraction levels and simulation test vectors.‎ • Ability to implement your design solution on a commercially available digital Computer

    $55 (Avg Bid)
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    I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be

    $174 (Avg Bid)
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    4 ofertas
    8-bit Calculator 2 dias left

    A calculator has to bee designed using System Verilog. It includes designing ALU, memory and system controller.

    $145 (Avg Bid)
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    2 ofertas

    I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made --

    $155 (Avg Bid)
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    Code needs to be ported from Matlab to Verilog

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    5 ofertas

    ...already have this you can modify that but I need the code running on FPGA board after I download it to it. Description: You have to create the VHDL model for the 4-bit multiplier. You must also synthesize the VHDL model, download to FPGA and test your multiplier on the FPGA board. Use a push button on the DE10-Lite FPGA to provide the clk input to the

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    Make next address Block 11 horas left
    VERIFICADO

    You have to build an address block using VHDL

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    5 ofertas

    Verilog Task with Vivado and Quartus 2. Should be familiar with schematic design in Altera Quartus 2.

    $38 (Avg Bid)
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    5 ofertas

    hello, I have this project where I need to read from files and print the output in one file. I provided a very similar code , that can be modify and Matlab code to generate input files.

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    To stimulate a project-based evaluation approach using VHDL and write a report. More information is contained in the file. Projects need to be written in VHDL and run a simulation for the program using a board. I will need the VHDL code and simulation for the timing diagram.

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    3 ofertas
    AXI FULL FIFO debug Encerrado left

    I created this project and fini...created this project and finished the entire code ,but for some reason it is not giving me the correct outputs.I would like help to fix the issue by editing my code. using VHDL in vivado I was able to create successful circular cordic. but when I made my AXI full and run it in SDK, it did not give me the right answer

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    A task compromising of Counter, clock divider, clock enable (CE), and seven-segment display using VHDL and Xinlinx Vivado. Further details will be provided. Deadline 3 days.

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    ...with MAX10 10M50DAF484C7G FPGA * ____________ Final Products: ____________ -A software-level block diagram showing the connections between the System Verilog modules described in pdf -System Verilog implementations of the modules described in pdf. -Valid hardware output. Final Note: Please attach any necessary files with a brief description of the

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    1) Design a Finite State Machine (FSM) using Verilog to control the taillights of a 1965 Ford Thunderbird. 2) Implement your design on FPGA

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    3 ofertas

    ALU Design as per instructions in Verilog Task . Simulation done using Icarus VERILOG

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    ...ability to extract and critically evaluate data for an unfamiliar digital design problem.  The application of appropriate design methods to the VHDL design.  The selection appropriate analysis tools, VHDL model abstraction levels and simulation test vectors.  Ability to implement your design solution on a commercially available digital Computer Aided

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    5 ofertas

    am a master student, studying embbeded microelectronic and wireless systems, i need a vhdl code for dual_4_1 multiplexer, for structure, behaviour and dataflow if possiblr. thank you

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    15 ofertas

    I need someone to create video tutorials for VLSI design from basics to advanced concepts. Advanced Digital Design Concepts CMOS Logic fundamentals RTL Design with Verilog HDL's ASIC Design Systhesis Concepts ASIC Design Stratagies Static Timing Analysis Low power design implementation Design and power Constraints Perl/Shell Scripting EDA tools usage

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    Need someone who has the tools and/or ability to convert a relatively simple verilog (.v) file to liberty timing (.lib) format, and who can verify the resulting .lib file. If successful and painless, there will be more such projects.

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    3 ofertas

    This is a vhdl and C++ project. requires knowledge of both VHDL and C++

    $20 / hr (Avg Bid)
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    14 ofertas

    It is required to implement the lyra2z cryptographic algorithm on the FPGA. Series FPGA Ultrascale Kintex language Verilog. [login to view URL]

    $649 (Avg Bid)
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    9 ofertas

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

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    Expert on VHDL needed to integrate custome VHDL system in Vivado. He is also expected to create a custome SDK app that can handle this custom peripheral. Please bid if you can do. Due in 36 hours

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    3 ofertas
    VHDL expert needed Encerrado left

    Expert on VHDL needed to integrate custome VHDL system in Vivado. He is also expected to create a custome SDK app that can handle this custom peripheral. Please bid if you can do

    $25 (Avg Bid)
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    4 ofertas

    Hey, I have a project that needs to be done in Verilog and Vivado and I'll share details to anyone interested.

    $25 (Avg Bid)
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    8 ofertas

    Just need to design the Snake Gane as per my specifications. I am using Nexys 4 development board.

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    6 ofertas
    Project for Loi L. Encerrado left

    ...- language : VHDL - IDE : Quartus Prime Lite Edition - Simulations with ModelSim - mini-project : 0) implement a 1680x1050-60Hz mode VGA controller (operating @ 143Hz pixel clock via PLL) 1) store 280x280 8byte/pixel image to on-chip memory (M9k blocks) 2) read image from on-chip memory (using Altera/Intel's RAM-1Port vhdl IP) 3) output

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    i have attached the document below. And i need this on 21st of october.

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    ...have to be ported to VHDL and be integrated before programming the Xilinx V6 FPGA on the transmitter. Complete hardware and many of the software blocks in VHDL are already built by our team. The requirement is urgent. Entire work to be completed in 2 - 3 weeks. Any freelancer with experience in integrating system level codes in VHDL, basics of digital

    $863 (Avg Bid)
    Local
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    Need an expert in xilinx vivado Projects are based on digital systems on topics such as Multiplexers Flip flops registers Counters Clock dividers Please contact for project instructions and further details

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    Snake Game : 1.) Should run on Altera DE2 Board or on basy3 . 2.) Should Support VGA. 3.)Needed in a 3 days. skills:- verilog software:vivado i need this project in verilog and not in VHDL

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    Task on verilog 3 bit ALU Deadline 1 day Amount USD 40

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    22 ofertas

    Need a small task on 3 bit ALU using verilog. Deadline 18 hours amount usd 30 .

    $28 (Avg Bid)
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    3 ofertas
    Distance using FPGA Encerrado left

    I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data

    $117 (Avg Bid)
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    21 ofertas

    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

    $16 / hr (Avg Bid)
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    30 ofertas

    I have project ready already just need some help!

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    9 ofertas