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    6,288 verilog ascii trabalhos encontrados, preços em USD

    Boa tarde, Lívia! Gostaria de ter a sua consultoria para o meu projeto, que consiste em integrar um processador (construído em verilog) a um Gerenciador de processos. No entanto, o prazo é apertado: dia 22/02 terça-feira. Não tenho problema com pagar a mais.

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    Boa tarde, Canisio! Gostaria de ter a sua consultoria para o meu projeto, que consiste em integrar um processador (construído em verilog) a um Gerenciador de processos. No entanto, o prazo é apertado: dia 22/02 terça-feira. Não tenho problema com pagar a mais.

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    Boa tarde, Nilson! Gostaria de ter a sua consultoria para o meu projeto, que consiste em integrar um processador (construído em verilog) a um Gerenciador de processos. No entanto, o prazo é apertado: dia 22/02 terça-feira. Não tenho problema com pagar a mais.

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    Boa tarde, Iaçanã! Gostaria de ter a sua consultoria para o meu projeto, que consiste em integrar um processador (construído em verilog) a um Gerenciador de processos. No entanto, o prazo é apertado: dia 22/02 terça-feira. Não tenho problema com pagar a mais.

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    Elevador duplo Encerrado left

    I need a Verilog code simulating two 7-storey elevators, where the elevator that will arrive will be the closest to the floor it was called. I can give more information about the project privately. Preciso que seja feito um código Verilog simulando dois elevadores de 7 andares, onde o elevador que chegará será o mais próximo do andar que o mesmo foi chamado. Posso dar mais informações do projeto de forma privada.

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    Olá Nilson E., eu vi seu perfil e gostaria de lhe oferecer meu projeto, preciso que seja feito um código Verilog simulando dois elevadores de 7 andares, onde o elevador que chegará será o mais próximo do andar que o mesmo foi chamado. Posso dar mais informações do projeto de forma privada.

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    Criar um processador em verilog, contendo as especificações citadas no pdf.

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    O freelancer deverá conhecer as linguagens = C / vhdl / verilog e já ter trabalhado com FPGA / ASIC Portar e otimizar um código que já tenho pronto em "c" para vhdl ou verilog esse código gera uma string de 14 / 15 dígitos, será usado uma placa fpga xillinx spartan 6 ( a empresa xillinx disponibiliza todo o ambiente necessário ). converter a string em Sha256 usando placa asic depois de convertido em sha256 compara com um sha256 informado no inicio do processo, se igual finaliza, se não reinicia o processo. Deverá ser usado a Raspberry Pi 3 para termos uma interface ( teclado e monitor ) para inserir o código inicial

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    Implementar um jogo em verilog ou vhdl em vga

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    Jogo VGA em Verilog para FPGA

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    VHDL/verilog Encerrado left

    Segue trabalho em anexo

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    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

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    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

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    Tenho um programa de "Cálculo de Lajes pelo Método da Ruptura" de minha autoria já em uso e comprovadamente funcional e autoexplicativo (para Engenheiros Civis)<br />Este programa só roda no DOS do Windows XP em Turbo Basic 1.0 (TB) da Borland (com compilador interno bastando apertar um botão) <br />DESAFIO transforma-lo para Visual Basic a partir do TB com desenhos fora de escala pela tabela ascii<br />posso fornecer:<br />O programa em TB extensão .exe e os programas fontes bem como o para rodar os programas fontes o que irá facilitar a conversão<br /> 

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    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três estágios acessam componentes críticos de hardware: o CDB, as estações de reserva (nas quais ocorrem as renomeações) e as unidades funcionais. Você deverá implementar: (1) as estações de reserva, (2) os estágios do algoritmo, (3) as unidades funcionais de multiplicação/divisão e soma/subtração, (4...

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    ...quem envie comandos para abertura e fechamento de uma catraca. Com a function pronta, colocaremos em um site online que devera se comunicar com a catraca de uma clube de esportes e liberar ou fechar o acesso. Mas isso será a segunda etapa, agora preciso amenas da function e testar seu funcionamento bem simples pelo código mesmo. A catraca opera por meio de linhas de comando, em texto puro (ASCII), disparadas direto para o equipamento (via TCP/IP). A operação na TCP/IP se dá por sockets, podendo o software trabalhar como Server ou client, por meio de diferentes portas. O equipamento emite mensagens somente em caso de solicitação de acesso e recebe qualquer comando em qualquer momento, não necessitando de efetuar pool...

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    ...pedir ao utilizador um número inteiro. Em vez de  utilizar a chamada ao sistema de código 1 irá utilizar um ciclo e a chamada ao sistema de código  12 (leitura de um caracter1 ) e armazenar os caracteres digitados num array. Se o utilizador  introduzir um caracter não-válido (por exemplo, uma letra) o programa mostra uma mensagem  de erro e começa tudo de novo. O "Enter" (código ASCII 10) deve ser reconhecido como o sinal  de que o utilizador acabou de digitar o número. Não esquecer de terminar a string com um zero.  No fim o número introduzido (armazenado na string) deverá ser mostrado com a chamada ao  sistema de código 4.    Exemplo ...

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    Preciso converter arquivos EBCDIC (Mainframe) para ASCII (micro). Quero um software de conversão de tipo de dados. O arquivo de origem é tipo texto e saída também será texto. Trata-se de um conversor de base EBCDIC (mainframe) para o ASCII (micros).

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    I need to implement a complete FPGA system using Verilog in Vivado Design Suite. Professional FPGA experts are required. Please find the details of the project in the attachment.

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    FEC RS(198, 194) 5 dias left

    Verilog FPGA Code implementation of FEC RS(198, 194) decoder.

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    I want go get help to implement FEC RS(198, 194)

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    Data acquisition software that allows to acquire, log and trend data from any device that supports Modbus/ASCII, OPC, WITS <WITSML/> and other protocols in the industry. 1. USER INTERFACE User friendly Intuitive user interface carefully designed to balance between simplicity and flexibility with minimum configuration from the user 2. CONNECTIONS Allows multiple connections simultaneously with support of many protocols including: Modbus TCP/IP, OPC Modbus serial RTU/ ASCII, ASCII stream WITS WITSML and more. 3. DISPLAYS & MONITORS Displays and monitors including digital displays, radial gauges, level gauges, grids, dynamic grids, process diagrams and trends. 4. PLOTS & TRENDS Fast performance trend supports millions of data with multiple axes sets (up to ...

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    Summary: Off the shelf micro based control unit using Arduino, etc. Unit takes 2 pulse inputs and interprets to speed, these are 5 volt PNP inputs. Unit has multiple relay outputs for alarms, 4-20 ma analog output, serial output (fixed length ASCII), Ethernet Modbus and Profibus interfaces (slave). The unit has no keypad nor display, programming wil be via bluetooth running an app on IPhone and Android devices. App writing is required. Unit has 2 modes of operation. Stand alone single pulse processing and differential detecting from 2 pulse inputs. Thru Hole and SMT, coding, testing and all drawings and source code.

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    I have a project that reads PNG Sprite files for ASCII character sets. I need a Delphi or Lazarus developer to help me make a DESKTOP editor for it User selects from a list provided by the web server - the list will be sequencial number of the existing FONT file. 0 equates to doing a GET (please look at this file, it is an existing font file). That file is 8px wide by 8px tell, per character. So to load "A" (ASCII 65), you copy top left (8*(65-1)) width 8px, height 8px. I would like your app to load said file(s) and display each character similar to Window's Character Map. If the user double clicks "A" for example, you load the above scenario - render it much larger. Use a 1 pixel clSilver border around each zoomed pixel - to make it obvious to

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    Code converter. Encerrado left

    A code converter is a software that is used to convert codes ...(data) from one programming language to another. There are many different types of code converters but the most popular ones are for converting from a high-level programming language like JavaScript or Python to a low-level language like C or Assembly. The code converter can be used for various purposes such as converting a binary file into ascii text or decimal into hexadecimal or hexadecimal to binary file. Alright the job here is simply convertion of some ascii text into binary file, more information will be sent to you as we proceed further with the project. Interested candidates should kindly contact our company administrative team member via telegram @DebraMcCann. For further information on the project and ...

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    5G RAN FPGA Design Encerrado left

    We have an internal project for 5G RAN FPGA design for DFE products: Skills: Job Description- Senior MTS RTL design 5G Product( 2 positions) · Candidate must have at least Bachelors or Masters EE - FPGA design experience (RTL Coding, comms, DFE(DPD, DUC, DDC, FFT, FIR, CFR) · Candidate must have verifiable experience for a minimum 6 years as a Verilog/System Verilog/ VHDL/RTL programmer with extensive Verification test bench development experience · Preferred prior project experience in 5G ORAN - RU/DU. DSP knowledge Matlab modeling is preferred. · eCPRI experience preferred . Special consideration will be given to those who have experience as 100G Ethernet or 10G Ethernet , IEEE 1588 · Knowledge of Queuing theory · Tools &nd...

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    I want you to desgin an IC chip description document. I need you to understand the verilog design and create some design descriotions, describing its fucntions in detail. The chip design has 3 main blocks ADC, PMU and sensors. These 3 blocks contain the most important functions of this chip. Please bid if you are experienced in wrting technical design documents for chip desing in detail. Thanks!

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    ASCII C Task Encerrado left

    Tasks done in C Programming. You are creating an number output based on grabbing inputs from the ASCII

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    a file would be provided in which improvement and development are required. Modify the files to accept binary PGM and ASCII, and write utilities called pgma2b to convert the ASCII form to binary. pgmb2a to convert the binary form to the ASCII.

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    function storeDocument(document, documentNumber) { // TODO implement } function performSearch(search) { // TODO implement } (); ("ascii"); let input = ""; ("data", function (chunk) { input += chunk; }); ("end", function () { // now we can read/parse input const lines = ('n'); let index = 0; const N = parseInt(lines[index++]); for (let i = 0; i < N; i++) { storeDocument(lines[index++], i) } const M = parseInt(lines[index++]); for (let j = 0; j < M; j++) { (performSearch(lines[index++])) } });

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    I have the code for I2C slave. I want help in writing the verilog code for I2C Master testbench to communicate with the given slave. It can send a few i2C write and read commands (with address, data, etc). I have attached the code for I2C slave alonside for your reference.

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    Draw geometric shapes with ASCII characters in console/terminal mode with C language. Firstly you can use "*" to draw shapes Step 1 create function to draw rectangle with fixed parameters (6x10) Step 2 improve function draw rectangle to accept parameters (length, width) Step 3 improve the function draw rectangle to draw by adding two modes: only borders or filled Step 4 create function to draw square with parameters (size, mode) Step 5 create function to draw any shapes (rectangle or square) Step 6 create function to draw right triangle with fixed parameter (height) Step 7 create function to draw equilateral triangle with fixed parameter (height) Step 8 implement all triagles shapes into draw shapes function (step 5) Step 9 improve draw rectangle if only borders ...

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    Convert csv to XML Encerrado left

    I converted my original XML data file to a csv file using Python 2.7.9. I then created a Python csv2xml program to convert the new csv database ...original XML data file to a csv file using Python 2.7.9. I then created a Python csv2xml program to convert the new csv database back into a new XML file that matches exactly the original XML. I can't get my csv2xml program to work. I need someone to fix my code so it works as I intended. After you get my csv2xml program to work, the newly created XML file must match exactly the original XML using ascii hex comparison. Each imported record must be cleaned using hex editing code to ensure all imported records records match the original exactly. Attached are both my original XML and created csv files. My is available upon reque...

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    Your job is to write verilog code for i2c communication and interface it with a processor. Take data from the slave through the accelerator and store it in a memory. Make the processor read the data from that memory and give its response. Now write that response data back to the slave.

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    SOC Verification Encerrado left

    ...ARM Interconnects(AHB, APB), SPI, UART, I2C, DMA, Serial Flash, Security and Encryption. 3. Full chip SoC (C and SV based), Subsystem and Block/IP level verification. Test Bench generation with ability to run embedded C programs. Must have experience of 2-3 SoC verification. 4. Experience in HDL(Verilog, VHDL) and HVL(System Verilog, Specman) based functional verification. Experience in code coverage. 5. Experience in Verification methodologies(UVM, OVM and eRM). language simulation (Verilog-AMS, SystemVerilog). 7. Experience in Mentor, Cadence and Synopsys simulators. 8. Build automated Test bench and regression environments from a scratch. Should be able to write a test plan and generate test cases 9. Regression management and Verification Sign-off based on Funct...

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    I need Verilog code for Energy-Efficient Logarithmic Square Rooter. It should be done within 1-2 days maximum.

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    I am looking to develop a Verification Code using System Verilog for USB 2.0 Protocol and also I want a verification plan for that . Kindly note that I want Complete TB code for all the components in Environment and also Test and Top instances as well . For any query/ or clarity ping me.

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    A complete color sorter Machine Firmware needs to be converted into Intel Quartus Project, The project contains IP Cores as well as softcore processor and the verilog coding part, All these to be integrated as a single bit file and to be implemented it on a Cyclone V FPGA Board.

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    I'm looking to have a program made that will receive ASCIi commands through the RaspberryPi 4 USB port to display either an image or video on command, and also have an optional menu that will be on demand by ASCIi command as well.

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    ...first line describes the edges of the graph o Each edge is formatted as an opening bracket '[', the first node of the pair, a comma, the second node in the pair, another comma, the distance between the nodes, followed by a closing bracket ']'. Example: '[A,B,5]. the second line describes the start and destination node, as well as the maximum allowed travel time the starting node, followed by an ascii arrow '->(two characters), the destination node, a comma, and the maximum allowed travel time. Example 'A ->D,5 - Leading or trailing whitespace is not allowed - All nodes are single, uppercase letters. - Edges are separated by a single space. - Distances are specified as unsigned integers - The sequence of edges is not ordered in any speci...

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    We need a project done in Morse code encoder and decoder in VHDL. Our project contains 2 parts a transmitter and receiver. The transmitter part receives the text(ASCII) from the PC(user) via UART receiver and transmits the text to morse code encoder(converts text to morse code). The morse code pattern then is sent to an led. Dot(.) corresponds to LED on and dash(-) LED off. The receiver part has a photo diode which reads the blinking of the led(morse code) and data is transmits to Morse decoder where it is converted back to ASCII. The converted ASCII is then transmitted to end user PC for display. We have already designed the top level top level block diagram. we now need the source codes(entity and architecture) for the blocks and test benches for all blocks for simul...

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    FPGA Project Encerrado left

    I need to do simple FPGA project on Boolean Board (Real Digital). For example Tic Tac Toe game. software should be Vivado and programming should be done in Verilog.

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    Use a Java properties file (*.properties) for English reference. It has around 200 property keys. There is no interpolation. Some property values have HTML formatting. Deliver a Java properties file (*.properties) with Thai translations. This properties file should be encoded using ISO-8859-1. That means that you will need to use native-to-ascii conversion to encode the Thai characters.

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    STM32F4 referenced boards : Nucleo-64 STM32F411 or STM32F410. Gyroscope and Magnetometer board: Adafruit LSM303AGR. Using one of 2 above Nucleo boards, connected to the Adafruit LSM303AGR via I2C bus, develop the firmware in the STM32F4 chip for... 1) Read Gyroscope and Magnetometer data from a serial connection with a host PC. This will be done using an ASCII protocol from a simple application like YAT (serial COM 115200@8N1). 1.1) Read data from the Gyroscope 1.2) Read data from the Magnetometer 1.3) Every N seconds print the Gyroscope data. And command to stop this loop. 1.4) Every N seconds print the Magnetometer data. And command to stop this loop. 2) Perform the Gyroscope and Magnetometer calibrations. The Gyroscope and Magnetometer calibrations could be done following ...

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    Modelling and texturing a character for a videogame project. Software skills required: Zbrush - Maya - Mari Delivery files: ZTL, Zbrush project, Maya ASCII file, PSD textures IP and NDA agreements required to be signed. Concept art will be provided after paperwork. The freelance will not be authorised to publish, sell or use the assets. Send your best work to be considered. Example of quality and complexity attached

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    I'm looking to have a program made that will receive ASCIi commands through the RaspberryPi 4 USB port to display either an image or video on command, and also have an optional menu that will be on demand by ASCIi command as well.

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    I'm looking to have a program made that will receive ASCIi commands through the RaspberryPi 4 USB port to display either an image or video on command, and also have an optional menu that will be on demand by ASCIi command as well.

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    I'm looking to have a program made that will receive ASCIi commands through the RaspberryPi 4 USB port to display either an image or video on command too two HDMI screens, and also have an optional menu that will be on demand by ASCIi command as well.

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    Explain and help understand Ethernet MAC/PHY RTL from github. Required: - Industry experience in digital/mixed-analog IP RTL design, preferably Ethernet IP. Meetings will be conducted via zoom/meets. Thank you!

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    I'm looking to have a program made that will receive ASCIi commands through the RaspberryPi 4 USB port to display either an image or video on command, and also have an optional menu that will be on demand by ASCIi command as well.

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