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    2,730 verilog vhdl trabalhos encontrados, preços em USD

    Implementar um jogo em verilog ou vhdl em vga

    $140 (Avg Bid)
    $140 Média
    6 ofertas

    Jogo VGA em Verilog para FPGA

    $154 (Avg Bid)
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    3 ofertas
    VHDL/verilog Encerrado left

    Segue trabalho em anexo

    $147 (Avg Bid)
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    10 ofertas
    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

    $26 (Avg Bid)
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    3 ofertas

    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    $434 (Avg Bid)
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    2 ofertas
    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três está...

    $472 (Avg Bid)
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    3 ofertas

    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são

    $2065 (Avg Bid)
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    ...para formar uma palavra de 32 bits. Os sinais de controle m1, m2, m3, wPC, wMem, wRI devem ser associados às chaves de entrada. Um arquivo comprimido com todos os módulos VHDL do MIPS multiciclo é disponibilizado no Moodle. O código MIPS a ser carregado na memória está contido no arquivo mem.mif. Para exibição dos dados nos ...

    $96 (Avg Bid)
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    3 ofertas

    Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do có...

    $309 (Avg Bid)
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    1 ofertas

    Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am

    $154 (Avg Bid)
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    4 ofertas
    PRESENT-80 5 dias left

    Hi there! I'm based in Ahmedabad, India. This project is related to lightweight cipher, cryptography. I have attached a pdf containing information relevant to this project w...design so that I can perform power analysis on it. Need the code properly working in two days. I looking for a Clock based implementation on existing design Language used : VHDL

    $61 (Avg Bid)
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    5 ofertas

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found...clock based design so that I can perform power analysis on it. Need the code properly working in two days. Note: Clock based implementation on existing design Language used : VHDL

    $30 (Avg Bid)
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    2 ofertas

    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

    $4447 (Avg Bid)
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    23 ofertas

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    $390 (Avg Bid)
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    3 ofertas

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be ...individual modules are successfully executing but the final result doesn't appear which you can help me in debugging the same ) Note: Problem in debugging the code Language used : VHDL

    $158 (Avg Bid)
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    9 ofertas

    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

    $65 (Avg Bid)
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    18 ofertas
    need expert on VHDL Encerrado left

    expert on VHDL is need for a project on digital thermostat. This is a simple task. expert only should bid

    $75 (Avg Bid)
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    20 ofertas

    build a communication block in VHDL at Xilinx environment

    $402 (Avg Bid)
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    14 ofertas

    Implement Communication VHDL Comm port on Xilinx FPGA part

    $126 (Avg Bid)
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    16 ofertas
    Task in VHDL Encerrado left

    i have a task related to Communication VHDL Xilinx, i will share the details in chat.

    $115 (Avg Bid)
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    19 ofertas

    FPGA TCPIP implementation using Verilog

    $21 / hr (Avg Bid)
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    16 ofertas

    Verilog digital logic deisgn simple work

    $23 (Avg Bid)
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    18 ofertas

    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [login to view URL]

    $46 (Avg Bid)
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    16 ofertas
    i neeb vhdl project Encerrado left

    i need vhdl project for fpga bord i need skeleton and can move

    $24 (Avg Bid)
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    14 ofertas

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

    $23 (Avg Bid)
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    22 ofertas

    Need help developing a face detection system with the DE2-115 board and OV7670. I already developed the code for the face detection but in MatLab.

    $220 (Avg Bid)
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    14 ofertas

    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

    $22 (Avg Bid)
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    17 ofertas

    i want to realize the transfer function on fpga so any one with knowledge of vhdl and quartus tool can bid Thank you

    $37 (Avg Bid)
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    6 ofertas
    vhdl project Encerrado left

    I need you to implement a vcdl design project

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    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

    $21 / hr (Avg Bid)
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    ...in der Digital- / Analotechnik - Kenntnisse von Simulations- und Prüfumgebungen - Kenntnisse mit technischer Dokumentation/Nachweisführung. Technisch: - OrCAD, PSpice, FPGA/VHDL, C++ - DO-254, MIL-STD-1553...

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    3 ofertas

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    $131 (Avg Bid)
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    19 ofertas

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    $122 (Avg Bid)
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    13 ofertas
    Tic Tac Toe in VHDL Encerrado left

    I am looking someone who can fix the errors of the game tic tac toe in VHDL for DE2-115 and prepare report.

    $75 (Avg Bid)
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    4 ofertas

    We are looking for a System Verilog Training for few Engineers in our premises.

    $1988 (Avg Bid)
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    5 ofertas

    I need you to develop some VHDL designs for me. I would like this software to be developed in VHDL hardware descriptive language. With a  VHDL design and simulation

    $251 (Avg Bid)
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    3 ofertas

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    $100 (Avg Bid)
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    8 ofertas

    this is my brief description of my project and please only serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e P...

    $366 (Avg Bid)
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    2 ofertas

    firstly i am posting this second time because the guy called https://www.freelancer.com/u/ahmedmohamed85?ref_project_id=17168255 (Ahmedmohamed85) has showed is arrogance and negligence after accepting my project and asked me to create a milestone and cancelled it and made me to wait for 3 days without answering please guys kindly dont get fooled with such experienced guys and ruin your money and t...

    $58 - $140 / hr
    $58 - $140 / hr
    0 ofertas

    i will explain in brief when we discuss

    $16 / hr (Avg Bid)
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    12 ofertas

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    $122 (Avg Bid)
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    19 ofertas
    VHDL coding Encerrado left

    HDL coding from block diagram and pseudo algorithm

    $25 (Avg Bid)
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    5 ofertas
    Alarm clock Verilog Encerrado left

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    $184 (Avg Bid)
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    15 ofertas

    Develop a musical bell that will play a selected and programmed song in the FPGA.

    $86 (Avg Bid)
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    4 ofertas

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    $86 (Avg Bid)
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    5 ofertas

    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    $106 (Avg Bid)
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    11 ofertas

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow)...implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    $132 (Avg Bid)
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    7 ofertas
    VHDL expert needed Encerrado left

    Expert in VHDL needed to work on a code

    $13 / hr (Avg Bid)
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    14 ofertas
    Code Conversion Encerrado left

    Small project to write in VHDL

    $111 (Avg Bid)
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    24 ofertas