Filtro

Minhas pesquisas recentes
Filtrar por:
Orçamento
para
para
para
Tipo
Habilidades
Idiomas
    Estado do Trabalho
    2,773 verilog vhdl trabalhos encontrados, preços em USD

    Implementar um jogo em verilog ou vhdl em vga

    $140 (Avg Bid)
    $140 Média
    6 ofertas

    Jogo VGA em Verilog para FPGA

    $154 (Avg Bid)
    $154 Média
    3 ofertas
    VHDL/verilog Encerrado left

    Segue trabalho em anexo

    $147 (Avg Bid)
    $147 Média
    10 ofertas
    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

    $26 (Avg Bid)
    $26 Média
    3 ofertas

    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    $434 (Avg Bid)
    $434 Média
    2 ofertas
    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três está...

    $472 (Avg Bid)
    $472 Média
    3 ofertas

    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são

    $2065 (Avg Bid)
    $2065 Média
    2 ofertas

    ...para formar uma palavra de 32 bits. Os sinais de controle m1, m2, m3, wPC, wMem, wRI devem ser associados às chaves de entrada. Um arquivo comprimido com todos os módulos VHDL do MIPS multiciclo é disponibilizado no Moodle. O código MIPS a ser carregado na memória está contido no arquivo mem.mif. Para exibição dos dados nos ...

    $96 (Avg Bid)
    $96 Média
    3 ofertas

    Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do có...

    $309 (Avg Bid)
    $309 Média
    1 ofertas
    Verilog Task on Nexys 4 board 6 dias left
    VERIFICADO

    Just need to design the Snake Gane as per my specifications. I am using Nexys 4 development board.

    $72 (Avg Bid)
    $72 Média
    4 ofertas

    ...- language : VHDL - IDE : Quartus Prime Lite Edition - Simulations with ModelSim - mini-project : 0) implement a 1680x1050-60Hz mode VGA controller (operating @ 143Hz pixel clock via PLL) 1) store 280x280 8byte/pixel image to on-chip memory (M9k blocks) 2) read image from on-chip memory (using Altera/Intel's RAM-1Port vhdl IP) 3) output

    $50 / hr (Avg Bid)
    $50 / hr Média
    1 ofertas

    i have attached the document below. And i need this on 21st of october.

    $120 (Avg Bid)
    $120 Média
    7 ofertas

    ...have to be ported to VHDL and be integrated before programming the Xilinx V6 FPGA on the transmitter. Complete hardware and many of the software blocks in VHDL are already built by our team. The requirement is urgent. Entire work to be completed in 2 - 3 weeks. Any freelancer with experience in integrating system level codes in VHDL, basics of digital

    $835 (Avg Bid)
    Local
    $835 Média
    9 ofertas

    Need an expert in xilinx vivado Projects are based on digital systems on topics such as Multiplexers Flip flops registers Counters Clock dividers Please contact for project instructions and further details

    $134 (Avg Bid)
    $134 Média
    9 ofertas

    Snake Game : 1.) Should run on Altera DE2 Board or on basy3 . 2.) Should Support VGA. 3.)Needed in a 3 days. skills:- verilog software:vivado i need this project in verilog and not in VHDL

    $78 (Avg Bid)
    $78 Média
    5 ofertas

    Task on verilog 3 bit ALU Deadline 1 day Amount USD 40

    $63 (Avg Bid)
    $63 Média
    22 ofertas

    Need a small task on 3 bit ALU using verilog. Deadline 18 hours amount usd 30 .

    $28 (Avg Bid)
    $28 Média
    3 ofertas
    Distance using FPGA Encerrado left

    I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data

    $117 (Avg Bid)
    $117 Média
    21 ofertas

    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

    $16 / hr (Avg Bid)
    $16 / hr Média
    30 ofertas

    I have project ready already just need some help!

    $194 (Avg Bid)
    $194 Média
    9 ofertas

    Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix it.

    $19 (Avg Bid)
    $19 Média
    6 ofertas

    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

    $33 (Avg Bid)
    $33 Média
    3 ofertas

    risc processor design and test, more detail I will provide on chat

    $106 (Avg Bid)
    $106 Média
    16 ofertas

    Create a custom SPI master controller with single, dual, and QUAD operation modes in VHDL for a MAX V CPLD.

    $391 (Avg Bid)
    $391 Média
    9 ofertas

    we need a technical content writer who knows the system Verilog, OVM and UVM.

    $140 (Avg Bid)
    $140 Média
    7 ofertas

    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

    $121 (Avg Bid)
    $121 Média
    17 ofertas

    We are looking for C++ programmer with experience in building GUI using QT. Preferable EDA/ Verilog Experience with background in Electrical Engineering

    $500 (Avg Bid)
    $500 Média
    15 ofertas

    Please refer the att...the attached document. This is the base paper of my project. I want to do my project on 64 bit square root carry select adder. I request you to help me with the coding in Verilog using Xilinx in gate level or switch level modelling. Can you please share the cost and the time line for the code. I will need it as soon as possible.

    $43 (Avg Bid)
    $43 Média
    13 ofertas

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $176 (Avg Bid)
    $176 Média
    12 ofertas

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $149 (Avg Bid)
    $149 Média
    4 ofertas

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like ...Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    $414 (Avg Bid)
    $414 Média
    2 ofertas
    Vhdl LCD finctional Encerrado left

    In ready projekt on vhdl (tic tac toe game) I need to add state od the gamę on LCD [login to view URL]

    $32 (Avg Bid)
    $32 Média
    5 ofertas
    DSP48E1 help Encerrado left

    Hi! I need some help with DSP48E1 verilog instantiation.

    $4 / hr (Avg Bid)
    $4 / hr Média
    5 ofertas

    I need to write a VHDL code for transfer data from 2 zedboard using ethernet without using a zynq-processor

    $208 (Avg Bid)
    $208 Média
    12 ofertas
    I want clients Encerrado left

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

    $18 (Avg Bid)
    $18 Média
    2 ofertas

    I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.

    $18 / hr (Avg Bid)
    $18 / hr Média
    10 ofertas

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    $152 (Avg Bid)
    $152 Média
    7 ofertas

    add memory protection into the operating system, This project needs both hardware and software knowledge, you will be creating / implementing OS functions on the PicoBla...hardware and software knowledge, you will be creating / implementing OS functions on the PicoBlaze, programming in assembler. You may also need to modify the hardware using VHDL.

    $520 (Avg Bid)
    $520 Média
    10 ofertas

    Hello guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image table in the files section. Thank you a lot...

    $111 (Avg Bid)
    $111 Média
    1 ofertas

    Hello guys I...cache memory). I would comments on the code and the resulting image as deliverables. 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works. Again comments on the code please. P.S.: 8 by 8 vhdl integer divider I attach the image table in the files section. Thank you a lot for your bidding :)

    $25 (Avg Bid)
    $25 Média
    2 ofertas

    écrire un code vhdl , pour DE0 nano , permettant de lire la température a partir d'une entrée analogique avec un LM19 et en sortie il faut emmètre des son avec un buzzer ( différent fréquence en fonction de la température )

    $36 (Avg Bid)
    $36 Média
    2 ofertas

    Hello guys I will ...language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory) 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works I attach the image table in the files section. Thank you a lot for your bidding :)

    $28 (Avg Bid)
    $28 Média
    3 ofertas

    I need help with the structural in Xilinx. I will give you full details. Regards

    $24 (Avg Bid)
    $24 Média
    23 ofertas

    ...am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

    $38 (Avg Bid)
    $38 Média
    111 ofertas

    Hi, my name is Paride, nice to meet you. i have got your conctact from Alessandro, a classmate. I am working on a easy Vhdl project, i already wrote all the code, the simolulation is working, but i need your help for two fast tasks: • I need to assign the pins on my FPGA, i can't find the correct pin of 2 serial signals. • i need you to check if the

    $58 (Avg Bid)
    $58 Média
    1 ofertas
    verilog project Encerrado left

    verilog coding using putty or terminal. if you are interested i will give more information.

    $135 (Avg Bid)
    $135 Média
    27 ofertas
    System verilog Encerrado left

    I want help with system Verilog coding. I have a working code that I want revised a bit.

    $97 (Avg Bid)
    $97 Média
    8 ofertas
    ADC - VHDL Implement Encerrado left

    Implement an AD2949 IC input block and some more

    $530 (Avg Bid)
    $530 Média
    11 ofertas
    verilog project Encerrado left

    mtech Verilog project

    $21 (Avg Bid)
    $21 Média
    19 ofertas

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    $180 (Avg Bid)
    $180 Média
    7 ofertas