Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).
Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são
...para formar uma palavra de 32 bits. Os sinais de controle m1, m2, m3, wPC, wMem, wRI devem ser associados às chaves de entrada. Um arquivo comprimido com todos os módulos VHDL do MIPS multiciclo é disponibilizado no Moodle. O código MIPS a ser carregado na memória está contido no arquivo mem.mif. Para exibição dos dados nos ...
Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do có...
Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found in the pages between 342 to 355. The code has already been developed but I'm unable to procure the final result. ( As i can see that the individual modules are successfully executing
will explain in detail when you bid
i want to realize the transfer function on fpga so any one with knowledge of vhdl and quartus tool can bid Thank you
...in der Digital- / Analotechnik - Kenntnisse von Simulations- und Prüfumgebungen - Kenntnisse mit technischer Dokumentation/Nachweisführung. Technisch: - OrCAD, PSpice, FPGA/VHDL, C++ - DO-254, MIL-STD-1553...
this is my brief description of my project and please only serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga
...showed is arrogance and negligence after accepting my project and asked me to create a milestone and cancelled it and made me to wait for 3 days without answering please guys kindly dont get fooled with such experienced guys and ruin your money and time. and this is my brief description of my project and please only serious people who would like to work
Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow)...implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.
Implement an algorithm in vhdl done in Matlab using System Generator
1. Create a top level VHDL file for the project. VHDL code should be well formatted and commented. 2. Add two instantiations of a sync counter to the top level that are customized for the horizontal and vertical sync signals 3. Adapt the tesbench from homework 2 to simulate the top level file. Simulations should be annotated to depict events important
Necesito hacer un programa en VHDL de un reloj (formato 24hs), con cronometro y con alarma. Cuando cambio a cada uno. no se debe perder la cuenta de la hora, cronometro o la alarma seteada. El reloj, la alarma y el cronometro se debe poder cargar/modificar manualmente. Detención y reinicio del cronometro. Cuando la hora del alarma coincida con el clock
Convert C code to VHDL for BDLC, see attached datasheet. C code is available from TI website (or I can provide). Need to convert code, which is based on document into VHDL. Deliverables: VHDL code + working testbench + block diagram Need to be knowledgeable in Motor Control, C/C++ and VHDL.
BId only if u can do only the second...dropping it and seeing it through a stereoscope lensIn perspective projection and the use of two center projection (off-axis projection) 2,Implement hardware system using vhdl language and xilinx 9.2i software And executed on spartan -3e linen The graphic is displayed on an external screen only the second Part
Write a VHDL code to use two ultrasonic sensors as detectors, placed one at entrance and other at exit of a parking space. When the ultrasonic detects a car, use a counter to count the cars entering and decrement when a car exits. There is an RGB led place at each gate (entry &exit) which is used to indicate opening and closing of gates. Entry gate
working with a grideye infrared sensor and looking to send the data through a wifi Cypress connection. We have some experience with this already but i am looking ...this so that we can work back and forth to get this up and running. I would like to send the data to a be read out with a Visual C sharp interface. Experience with FPGA and VHDL is a bonus
I require source code for the design and simulation verification of a calculator (Not + - / * operations) with slightly more experienced VHDL'ers can be selected for th...require source code for the design and simulation verification of a calculator (Not + - / * operations) with slightly more experienced VHDL'ers can be selected for this quick project
Design a 3-phase 500Hz FPGA based generator driving a quad-channel DAC (only 3 channels needed) such as the LTC 2624. The overall idea is that; following <RESET> a table of values representing a sine wave shall be stored internally and scan sequentially by the three output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No othe...
Hi, This project is for a team of VHDL expert and Java expert. I have a dev. FPGA board embedded the chip AD9764. This is the DAC. It embeds the chip ADS5522 too. This is the ADC. I already have a not-completed project written in vhdl including modules parts of this project. I need you to simulate and fix the data transmission part between the client
I'm currently a 4th year degree student undergoing a project to build a Multiplexed DDS using iCE40UP5K breakout board. Apart from the Multiplexed DDS core itself, an i2s module for a DAC chip, Encoder modules for control of waveform parameters and an LCD module are present. Functional verification is done and behavior in simulation is as expected.