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    3,883 vhdl verilog fpga trabalhos encontrados, preços em USD

    Implementar um jogo em verilog ou vhdl em vga

    $140 (Avg Bid)
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    6 ofertas

    Jogo VGA em Verilog para FPGA

    $154 (Avg Bid)
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    3 ofertas
    VHDL/verilog Encerrado left

    Segue trabalho em anexo

    $147 (Avg Bid)
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    10 ofertas
    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

    $26 (Avg Bid)
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    3 ofertas

    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    $434 (Avg Bid)
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    2 ofertas

    Olá Pedro, Você trabalho com FPGA (Zedboard) Xilinx? Preciso de um programa capaz de exibir a camera do Kinect em uma placa Zedboard.

    $100 (Avg Bid)
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    1 ofertas
    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três está...

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    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são

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    ...para formar uma palavra de 32 bits. Os sinais de controle m1, m2, m3, wPC, wMem, wRI devem ser associados às chaves de entrada. Um arquivo comprimido com todos os módulos VHDL do MIPS multiciclo é disponibilizado no Moodle. O código MIPS a ser carregado na memória está contido no arquivo mem.mif. Para exibição dos dados nos ...

    $96 (Avg Bid)
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    Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do có...

    $309 (Avg Bid)
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    1 ofertas

    Develope script in XILINX ISE FPGA using nexys 4 ddr card Language VHDL For calculator

    $25 (Avg Bid)
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    4 ofertas

    ...de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware

    $225 (Avg Bid)
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    Need to update VHDL and C-Code for change the communication from PCI-e to USB. The target is a Xilinx FPGA

    $627 (Avg Bid)
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    9 ofertas

    We are Hiring Good Programmer in FPGA, GPU, CUDA, MATLAB for our Company. (Removed by Freelancer.com Admin)

    $347 (Avg Bid)
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    The project is described in the uploaded file, however one can alter the project as long as keeping the equipments and the goal of the project intact

    $107 (Avg Bid)
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    5 ofertas

    Complete a design that includes most of the elements to be used in the CPU

    $118 (Avg Bid)
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    9 ofertas

    Hello i have a code of piano synthesizer using VHDL (vivado) and i want to understand it and fix it ... can you help me ?

    $12 / hr (Avg Bid)
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    1 ofertas
    Verilog code 3 dias left

    Please do what is in the paper and hand me the code, testing waveforms and synthesized diagrams

    $102 (Avg Bid)
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    5 ofertas

    ...ability to extract and critically evaluate data for an unfamiliar digital design problem.‎ • The application of appropriate design methods to the VHDL design.‎ • The selection appropriate analysis tools, VHDL model abstraction levels and simulation test vectors.‎ • Ability to implement your design solution on a commercially available digital Computer

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    ...be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created by using a logic block as RAM). Your CAD tool should attempt to find a solution that minimizes the area of the FPGA needed to fit each benchmark circuit....

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    ...be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created by using a logic block as RAM). Your CAD tool should attempt to find a solution that minimizes the area of the FPGA needed to fit each benchmark circuit....

    $496 (Avg Bid)
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    I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be

    $174 (Avg Bid)
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    8-bit Calculator 19 horas left

    A calculator has to bee designed using System Verilog. It includes designing ALU, memory and system controller.

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    I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made --

    $155 (Avg Bid)
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    Matlab to Verilog Encerrado left

    Code needs to be ported from Matlab to Verilog

    $119 (Avg Bid)
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    5 ofertas

    I need an FPGA selected and hardware design created for decoding of an MPEG-Transport Stream parallel interface from a DVB-T demodulator. The FPGA needs to decode the transport stream and extract the video data as well as any other data contained in the Transport stream, the FPGA must then extract a selected individual pixel, and its colours are extracted

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    ...you can modify that but I need the code running on FPGA board after I download it to it. Description: You have to create the VHDL model for the 4-bit multiplier. You must also synthesize the VHDL model, download to FPGA and test your multiplier on the FPGA board. Use a push button on the DE10-Lite FPGA to provide the clk input to the multiplier. The

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    You have to build an address block using VHDL

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    Custom FPGA Project Encerrado left

    This is a multi-part project for the Lattice MACHXO2-4000 LOGIC IC.

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    Looking for a developer to interface high speed TI DAC with virtex 7 FPGA. I am having DAC34H84 DAC and VC707 kit- and want to interface the same DAC with VC707 Hardware that i have is DAC34H84 and VC707

    $42 / hr (Avg Bid)
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    Hardware Design Encerrado left

    - schematic capturing; - PCB lay-outing; - production files generation, prototype bringing-up and troubleshoo...experience: mixed circuitry hardware design, digital interfaces: USB, ADC (120MHz), analog circuitry: impedance matching, ADC, frequencies up to 100MHz, clocking and sync schemes, FPGA/MCU and peripherals. Job Type: Contract Location: GTA

    $27 / hr (Avg Bid)
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    16 ofertas

    Verilog Task with Vivado and Quartus 2. Should be familiar with schematic design in Altera Quartus 2.

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    hello, I have this project where I need to read from files and print the output in one file. I provided a very similar code , that can be modify and Matlab code to generate input files.

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    To stimulate a project-based evaluation approach using VHDL and write a report. More information is contained in the file. Projects need to be written in VHDL and run a simulation for the program using a board. I will need the VHDL code and simulation for the timing diagram.

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    AXI FULL FIFO debug Encerrado left

    I created this project and fini...created this project and finished the entire code ,but for some reason it is not giving me the correct outputs.I would like help to fix the issue by editing my code. using VHDL in vivado I was able to create successful circular cordic. but when I made my AXI full and run it in SDK, it did not give me the right answer

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    A task compromising of Counter, clock divider, clock enable (CE), and seven-segment display using VHDL and Xinlinx Vivado. Further details will be provided. Deadline 3 days.

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    A simple boundary extraction project that involves eroding a binary image using morphological structuring element, and subtracting the outcome from the binary image to get boundaries.

    $214 (Avg Bid)
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    We are a Signal processing Company, we are looking for designing a Board which can take 2 Channels of 70 MHz Input, 2 Channels of Baseband Signal 10 MHz BW, ... 2 Channels of Baseband Signal 10 MHz BW, 2 Digital TTL Channels with 10 MHz Rate and Ethernet Port for data transfer. All the Inputs and Outputs have to be connected to an FPGA processor Zync.

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    We are looking for one freelancer to develop FPGA software for best mining algo using Xilinx FPGA VCU1525 card. You will have to program an FPGA card that I will provide, to work for crypto mining. Is necessary also customize mining software that works under Windows to by able to works with the FPGA. Software must have to be perfectly optimized.

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    ...also found in attached files * * Hardware used: DE10-Lite kit with MAX10 10M50DAF484C7G FPGA * ____________ Final Products: ____________ -A software-level block diagram showing the connections between the System Verilog modules described in pdf -System Verilog implementations of the modules described in pdf. -Valid hardware output. Final Note:

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    1) Design a Finite State Machine (FSM) using Verilog to control the taillights of a 1965 Ford Thunderbird. 2) Implement your design on FPGA

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    Hi ! I currently need pcb layout engineer to upgrade my personal fpga board. It previously used Spartan 3E FPGA PQFP (PQ208/PQG208) package using the power voltage of 3.3v, 2.5v, 1.2v ... I'd like to have it replaced by an Artix fpga (FG484/FGG484 Fine-Pitch BGA package), henceforth using the lower voltages of 3.3v, 1.8v, 1.0v The voltage regulators

    $262 (Avg Bid)
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    30 ofertas

    I would like to port Nueral network for image identification on PYNQ FPGA

    $533 (Avg Bid)
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    ALU Design as per instructions in Verilog Task . Simulation done using Icarus VERILOG

    $22 (Avg Bid)
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    ...ability to extract and critically evaluate data for an unfamiliar digital design problem.  The application of appropriate design methods to the VHDL design.  The selection appropriate analysis tools, VHDL model abstraction levels and simulation test vectors.  Ability to implement your design solution on a commercially available digital Computer Aided

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    5 ofertas

    am a master student, studying embbeded microelectronic and wireless systems, i need a vhdl code for dual_4_1 multiplexer, for structure, behaviour and dataflow if possiblr. thank you

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    more details will be given in the chat and it more of writing article on this, if you cant write article on this please dont place your bid

    $20 (Avg Bid)
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    The goal is to design a game on Xilinx FPGA. More details on chat. The deadline will be 3 days. Only serious bidders who can complete in 3 days should bid. No Excuses. Time wasters avoid bidding, please.

    $120 (Avg Bid)
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    Cryptocurrency Mining Application in C or C++ We are seeking a senior engineer/architect with experience working with cryptocurrency mining sys...engineer/architect with experience working with cryptocurrency mining systems to provide technical consultation and to implement (or guide implementation) of a mining application for an FPGA via MicroBlaze.

    $201 (Avg Bid)
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    4 ofertas