Vhdl verilog lexer trabalhos

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    4,088 vhdl verilog lexer trabalhos encontrados, preços em USD
    Elevador duplo Encerrado left

    I need a Verilog code simulating two 7-storey elevators, where the elevator that will arrive will be the closest to the floor it was called. I can give more information about the project privately. Preciso que seja feito um código Verilog simulando dois elevadores de 7 andares, onde o elevador que chegará será o mais próximo do andar que o mesmo foi chamado. Posso dar ...

    $55 (Avg Bid)
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    Olá Nilson E., eu vi seu perfil e gostaria de lhe oferecer meu projeto, preciso que seja feito um código Verilog simulando dois elevadores de 7 andares, onde o elevador que chegará será o mais próximo do andar que o mesmo foi chamado. Posso dar mais informações do projeto de forma privada.

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    Olá Nilson E., eu vi seu perfil e gostaria que você me ajudasse, preciso que seja feito um código em VHDL simulando dois elevadores de 5 andares, onde o elevador que chegará será o mais próximo do andar que o mesmo foi chamado. Posso dar mais informações do projeto de forma privada, mas é basicamente isso.

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    Preciso que seja feito um código no quartus prime II em VHDL simulando dois elevadores de 7 andares, onde o elevador que chegará será o mais próximo do andar que o mesmo foi chamado. Posso dar mais informações do projeto de forma privada, mas é basicamente isso. Deve conter waveform.

    $37 (Avg Bid)
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    2 ofertas

    Criar um processador em verilog, contendo as especificações citadas no pdf.

    $195 (Avg Bid)
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    6 ofertas

    O freelancer deverá conhecer as linguagens = C / vhdl / verilog e já ter trabalhado com FPGA / ASIC Portar e otimizar um código que já tenho pronto em "c" para vhdl ou verilog esse código gera uma string de 14 / 15 dígitos, será usado uma placa fpga xillinx spartan 6 ( a empresa xillinx disponibiliza todo o ambiente necessário ). ...

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    Implementar um jogo em verilog ou vhdl em vga

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    6 ofertas

    Jogo VGA em Verilog para FPGA

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    3 ofertas
    VHDL/verilog Encerrado left

    Segue trabalho em anexo

    $90 (Avg Bid)
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    10 ofertas
    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

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    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

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    1 ofertas
    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três estágios ac...

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    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são usados para controlar LEDs q...

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    O MIPS Multiciclo utiliza uma única memória para armazenar programa e dados. A memória é endereçada pelo PC ou pelo registrador na saída da ULA, através de um multiplexador, sendo as instruções lidas da memória transferidas para o Resitrador de Instruções – RI e os dados lidos transferidos para o Registrad...

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    Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do código e ...

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    I need help with my school work and would like someone to help me

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    What is DDFS , working of DDFS? Verilog/vhdl code for DDFS. I need some explanation and modification of the code.

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    Hi , I have a VHDL/Switching project which will be uploaded today. It has a time limit which is 1.5 hours but it will be prepared to finish at that time. Will you be available today at 14.00 in germany time? My budget is 35 dollars

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    Hi are you available at 14.00 in Germany time. We have worked before on a VHDL task this is my new account

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    Job Description :- Automate some Perl to System Verilog Files of a switch testbench. Automate for multiple configurations provided in Perl file. For one of the configurations, a reference testbench is provided. Write scripts to automate TB files such that it matches refernce config and generate for all other config. Make sure simvs are getting built and tests are run. Detailed Requirement :- ...

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    Hi , I have a VHDL/Switching project which will be uploaded today. It has a time limit which is 1.5 hours but it will be prepared to finish at that time. Will you be available today at 14.00 in germany time?

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    Job Description :- Develop Verification Component of PCIE and other protocol devices including Generators, Transactors, Drivers, Transmiter, Receiver and Transmit and Receive Packet Classes. Build Simvs, and develop and Run test-cases using these components. Detailed Requirement :- 1) Preference - Junior 0-4 years of experience engineer or senior around 10 plus years of experience. Experien...

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    I need someone with VHDL knowledge.

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    I need someone to help mi with VHDL

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    7 ofertas
    Senior FPGA expert required -- 2 4 dias left
    VERIFICADO

    I am looking for a senior fpga expert who have experience in fpga with verilog language experience

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    Senior FPGA expert required 4 dias left
    VERIFICADO

    I am looking for a senior fpga expert who have experience in fpga with verilog language experience

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    4 ofertas

    to design and implement a game clock on the DE1-SoC development board, using any of its on-board resources (buttons, switches, seven segment displays etc.). The game clock should have two modes of operation to allow the following variations: • The first mode of operation should give each player a fixed amount of time for the whole game. There should be a suitable indication if either player...

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    Vhdl project 3 dias left

    I have a vhdl project i need help with, its on finite state machine.

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    You are required to design and implement a game clock on the DE1-SoC development board, using any of its on-board resources (buttons, switches, seven segment displays etc.). The game clock should have two modes of operation to allow the following variations: • The first mode of operation should give each player a fixed amount of time for the whole game. There should be a suitable indication...

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    3 ofertas

    A verilog model needs to be modified to some requirements

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    VHDL software design and stimulation

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    Design of dual port ram having each port with different clocks and write enable of 4 [fazer login para ver a URL] the 23 states marching algorithm of the bist controller rtl this dual port ram should be instantiated then for this module verifcation should be done using UVM methodology or system verilog .with the insertion of MBIST how the verfication must be done for memory module

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    MESI is a cache coherence protocol. The verification of the protocol is to be done using System Verilog and UVM. The signals to verify is sent through the sequencer to the driver and through the virtual interface to the DUT. The assertion checks should be written in the testbench.

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    I'm looking for a FPGA Firmware engineer who has rich experience in FPGA and VHDL/verilog programming. The right candidate should have an experience in Matlab and HDL Coder. The board is Zynq FPGA controller. The project is to implemente a Xilinx partial reconfiguration model for an SDR on the AD9361-Z7035 with ADRV1CRR-BOB. Also should have telecommunication knowledge. Please bid with the ...

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    Design a GCD for two 4-bit numbers (in your lecture notes, we have already done this). It will output the binary value of the greatest common divisor of those two 4-bit numbers.

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    I am trying to implement some games in Verilog. I have an Arty S7-50 board and currently I am working on a game like the classic Snake. I am using a PS2 keyboard to control the direction and I am using VGA to display the image. I have some troubles with my code and I need someone to look at it and make it work and add some features. For more details please contact me.

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    vhdl/verilog code for direct digital frequency synthesizer based on look up table method.

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    In this project an implimentation of BT1120 using either verilog/VHDL is carried out. The priority includes working on standard defnition(SD) signals and the video stream flows in BT.656. In this work decoding of high defnition signals to be used for various application is carried out. The incoming 8/10 bit video is decoded into Y,Cb,Cr format and produces horizontal and vertical blanking pulses a...

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    VHDL software and hardware help and kind of tutoring if possible, please.

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    It includes helping with vhdl software and hardware. kind of tutoring if possible please

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    Verilog Tutoring Encerrado left

    Design in verilog using modelsim I have a code but it needs to be explained more and might need modification

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    I need a Yescrypt mining software for FPGA AWS F1 based probably on verilog or vhdl. There is already CPU miner in C for yescrypt/yespower and some verilog for Scrypt algorithm. I need a development of a AFI image to work with Amazon F1 FPGA instances. Let's say an Yescrypt ASIC.

    $30 - $250
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    - Must have excellent written and verbal communication in English. - Must have at least 1 year of experience in Technical recruiting. - Must have recruited candidates in : * Electronics: ASIC/FPGA/Verilog/Embedded/PCB/CAB * IT: React, Microserverices, Angular, Data Science, Cloud, etc. - Should be available at least 20 hours a week (Monday-Friday), 40 hours is highly preferred. - Good knowledg...

    $3 - $8 / hr
    Secreto ADC
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    4 ofertas

    All information will be shared on PM. Candence Viruoso, gpdk090, VHDL etc.

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    Verilog Devider Encerrado left

    Attached is the project, I also need a test bench for this

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    This is an ongoing project so further needs would be helpful, I need to make sure that my code is running well in Verilog and I need to understand what is in there, you don't have to be brilliant but at least you have the enough background

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    RISC-V assembly Encerrado left

    Design a 5-clock cycle 32-bit RISC-V CPU in Verilog (or SystemVerilog). The CPU should support all rv32i instructions (except for ECALL, EBREAK, FENCE and all CSR instructions).

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