Vhdl verilog outsourcing trabalhos

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    4,792 vhdl verilog outsourcing trabalhos encontrados, preços em USD

    Implementar um jogo em verilog ou vhdl em vga

    $140 (Avg Bid)
    $140 Média
    6 ofertas

    Jogo VGA em Verilog para FPGA

    $154 (Avg Bid)
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    3 ofertas
    VHDL/verilog Encerrado left

    Segue trabalho em anexo

    $147 (Avg Bid)
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    10 ofertas
    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

    $26 (Avg Bid)
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    3 ofertas

    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    $434 (Avg Bid)
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    2 ofertas
    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três está...

    $472 (Avg Bid)
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    3 ofertas

    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são

    $2065 (Avg Bid)
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    2 ofertas

    Somos uma empresa de consultoria que opera nas seguintes áreas de negócio: - Consultoria de gestão - Outsourcing administrativo e financeiro Procuramos uma parceria com um gestor comercial com experiencia comprovada na área comercial/vendas para liderar esta área funcional.

    $45 / hr (Avg Bid)
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    5 ofertas

    ...para formar uma palavra de 32 bits. Os sinais de controle m1, m2, m3, wPC, wMem, wRI devem ser associados às chaves de entrada. Um arquivo comprimido com todos os módulos VHDL do MIPS multiciclo é disponibilizado no Moodle. O código MIPS a ser carregado na memória está contido no arquivo mem.mif. Para exibição dos dados nos ...

    $96 (Avg Bid)
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    Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do có...

    $309 (Avg Bid)
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    1 ofertas

    hey, I saw your work on the vhdl fm radio and I want to know if you're willing to send that same project.

    $150 (Avg Bid)
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    1 ofertas

    The project goal is the implementation of a Verilog module to interface a high-speed ADC (250MSps) using DDR. The IO/delay shall be dynamically adjusted after reset thru a test pattern match using a test mode of the ADC. As part of the project a simulation test bench needs to be set-up to verify proper function of the interface.

    $1345 (Avg Bid)
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    13 ofertas

    This project write the Verilog to initialize and read frames from an image sensor with high quality through 8 LVDS. Requirements: Expert only for Verilog & validation simulation in Xilinx Vivado. I think you can finish this within a week if you are a Verilog expert. If you have experiences for this, please contact me sk [Removed by Freelancer

    $456 (Avg Bid)
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    8 ofertas

    I run an outsourcing company where I have a team of people from Marketing & Sales, Business Development & Consulting, Project Planning, Management & Coordination, Virtual Assistance, Sourcing and Web Development! I work in some of these areas myself, and coordinate. I am currently expanding my Team and looking to hire members of the Team on my backend

    $250 (Avg Bid)
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    1 ofertas

    Need a vhdl project on mips pipelined processor

    $130 (Avg Bid)
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    6 ofertas

    Hi olegkaravaev84, I noticed your profile and would like to offer you my SystemVerilog/Verilog FP{GA project. We can discuss any details over chat.

    $450 / hr (Avg Bid)
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    1 ofertas

    We're looking for someone with experience is sending data from an FPGA to a PC via a FT601 chip (made by FTDI) and saving the data to a binary file on the PC side.

    $40 / hr (Avg Bid)
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    8 ofertas

    an expert on FPGA and Verilog should bid only...

    $160 (Avg Bid)
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    12 ofertas
    Verilog Design 3 dias left

    I have one architecture, needs the RTL verilog code for the design to be made and followed by placement and routing to derive the power.

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    10 ofertas

    1. Vivado HLS fixed code optimization 2. Introduction of parallelism and pipeling 3. c-simulation, synthesis and RTL-C cosim verification 4. IP generation in Vivado HL... Introduction of parallelism and pipeling 3. c-simulation, synthesis and RTL-C cosim verification 4. IP generation in Vivado HLS 5. Intergration of IP generated in HLS in Verilog code

    $181 (Avg Bid)
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    1 ofertas

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design

    $115 (Avg Bid)
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    6 ofertas

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.

    $166 (Avg Bid)
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    7 ofertas

    I need some help with my business.

    $4 / hr (Avg Bid)
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    4 ofertas

    hi need some one to do android app , i have complete source code you need to edit it little bit , i am outsourcing. if u can do know let me know the the source code will genrate an apk file and connection to it php my admin panel so after setup u have generated apk and url of admin panel as all data comes from php my admin panel which we control the

    $52 (Avg Bid)
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    18 ofertas

    hi need some one to do android app , i have complete source code you need to edit it little bit , i am outsourcing. if u can do know let me know the the source code will genrate an apk file and connection to it php my admin panel so after setup u have generated apk and url of admin panel as all data comes from php my admin panel which we control the

    $90 (Avg Bid)
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    5 ofertas

    The brightness measurement with help of PMODALS sensor ([fazer login para ver a URL] one of the push buttons, the display should change between the display modes percent (0% -100%) and ADC value (0-255). I can send to you all necessary vhdl files for mc8051. Keywords: VHDL, C, SPI, mc8051, Basys3, FPGA, Ambient light sensor

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    6 ofertas
    Project for Jin C. 23 horas left

    Hi Jin, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    $160 (Avg Bid)
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    1 ofertas

    Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    $200 (Avg Bid)
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    1 ofertas

    Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    $160 (Avg Bid)
    $160 Média
    1 ofertas
    build mac unit Encerrado left

    build mac unit using verilog language. I have already done the multypler part and I need help to build the rest

    $38 (Avg Bid)
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    9 ofertas

    ...simple/minimal implementation using logic primitives (basic gates and flip flops). Secondly you are to produce a (more) fully capable design using VHDL. Both designs are to be verified by simulation. 6- The VHDL-based design should also be programmed into the FPGA on the development board and verified using the encoder hardware provided. More detailed specifications

    $410 (Avg Bid)
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    13 ofertas

    Basically I would like to have the verilog coding to build on my basys3 hardware. required to control the LED with left and right pushbutton within a range, to code different frequency for the LED within that range, to code one letter on each 7segment and the speed of the letter being displayed is depend on the frequency coded to the led. to code a

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    FPGA mining hardware - Xiling FPGA - Nexys Video - Can be leveraged from open source bitcoin miner code. - Based on Verilog. - Provide source code, constraints and full recipe for synthesis, implementation and bitstream generation - Connectivity via JTAG to the host (via USB). May consider UART instead, but as a less desirable solution. Mining software:

    $565 (Avg Bid)
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    8 ofertas

    we are doing some company research work right now would like to see if anyone could share database membership with us, any popular database would be fine , bloomberg, DB hoovers, etc, we could pay by week, by month thanks

    $177 (Avg Bid)
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    2 ofertas

    I have a VHDL source for the Altera EP3C25F256C8 FPGA design. I like an expert to setup the timing and fitting parameters to give the design optimum performance. I use Quartus II software version 8.1

    $282 (Avg Bid)
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    7 ofertas

    The distance measurement with help of MB1010 ultrasonic distance sensor ( https://www.maxbotix.co...displays. Pressing a button on the board should switch between inches, meters and centimeters. I can send to you all necessary vhdl files for mc8051. Keywords: Basys3, FPGA, Ultrasonic distance sensor, UART, mc8051 IP Core, VHDL, C, Vivado, ModelSim

    $272 (Avg Bid)
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    2 ofertas
    FPGA verilog Encerrado left

    Using ModelSim or Quartus II for solving some problems i am working on

    $27 (Avg Bid)
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    17 ofertas
    Project for Loi L. Encerrado left

    Hi Loi L., I noticed your previous work on the FIFO implementation of a FM Radio in VHDL. I was wondering if you would like to work on that same project. We can discuss any details over chat.

    $150 (Avg Bid)
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    1 ofertas

    The details of the design will be sent and discussed later. The freelancer needs to have proficient knowledge of VHDL and digital design. Only serious and professional freelancers needed

    $26 (Avg Bid)
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    NEED VHDL CODE Encerrado left

    I NEED VLSI CODE VHDL-7-5-Reed-Solomon ENCODER AND DECODER I HAVE SOME CODE JUST NEED TO RUN AND EXPLAIN MAKING SOME CORRECTIONS

    $16 (Avg Bid)
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    4 ofertas

    The brightness measurement with help of PMODALS sensor ([fazer login para ver a URL] )...buttons the display should change between the display modes percent (0% -100%) and ADC value (0-255). I can send to you all necessary vhdl files for mc8051. Keywords: Basys3, FPGA, Ambient light sensor, SPI, mc8051, VHDL, C, Vivado

    $180 (Avg Bid)
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    9 ofertas

    Code will contain encryption and decryption of elliptic curve cryptography

    $111 (Avg Bid)
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    1 ofertas

    In this project, a simple VGA (Video Graphics Array) controller shall be implemented using an FPGA Basys3. The VGA controller should be able to display images with a resolution of 640X480 pixels. Furthermore, it should be possible to select between two different images, depending on the position of switch SW1. Document description of whole design including images explanation of Testbench with...

    $110 (Avg Bid)
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    2 ofertas

    Hi, we have project for creating simple RISC processor through vhdl/Verilog. If interested will give more information

    $10 / hr (Avg Bid)
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    1 ofertas

    VHDL/Verilog basic RISC Processor, will give more details if interested

    $7 / hr (Avg Bid)
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    1 ofertas

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.

    $235 (Avg Bid)
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    21 ofertas

    This project consists to port some c code (around 50 lines) to Verilog in order to run on a FPGA. Output of the contest Verilog .v source file equivalent of verilog.c testbench .v file equivalent to doSimulation() You can run the C code with "gcc main.c && ./[fazer login para ver a URL]" Elements to select the winning bidder: - Partial screenshot of the implement...

    $67 (Avg Bid)
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    8 ofertas