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    5,868 vlsi verilog fpga asic trabalhos encontrados, preços em USD

    A presença de erros em dados digitais é um problema frequente em sistemas computacionais que lidam com transmissão e armazenamento de informação. Em alguns contextos, como o de computação aproximada, admite-se uma taxa ainda maior de erros para alcançar uma redução no consumo de energia. Nesses casos, torna-se imprescindível o controle de erros. Isto pode ser feito através do uso d...através do uso de códigos detectores (e corretores) de erros, que são capazes de detectar (e corrigir) a informação corrompida através de redundância inserida nos dados. Nesse projeto, o objetivo é gerar um codificador baseado em paridade e um detector de erros que avisa qu...

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    Boa tarde, Lívia! Gostaria de ter a sua consultoria para o meu projeto, que consiste em integrar um processador (construído em verilog) a um Gerenciador de processos. No entanto, o prazo é apertado: dia 22/02 terça-feira. Não tenho problema com pagar a mais.

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    Boa tarde, Canisio! Gostaria de ter a sua consultoria para o meu projeto, que consiste em integrar um processador (construído em verilog) a um Gerenciador de processos. No entanto, o prazo é apertado: dia 22/02 terça-feira. Não tenho problema com pagar a mais.

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    Boa tarde, Nilson! Gostaria de ter a sua consultoria para o meu projeto, que consiste em integrar um processador (construído em verilog) a um Gerenciador de processos. No entanto, o prazo é apertado: dia 22/02 terça-feira. Não tenho problema com pagar a mais.

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    Boa tarde, Iaçanã! Gostaria de ter a sua consultoria para o meu projeto, que consiste em integrar um processador (construído em verilog) a um Gerenciador de processos. No entanto, o prazo é apertado: dia 22/02 terça-feira. Não tenho problema com pagar a mais.

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    Elevador duplo Encerrado left

    I need a Verilog code simulating two 7-storey elevators, where the elevator that will arrive will be the closest to the floor it was called. I can give more information about the project privately. Preciso que seja feito um código Verilog simulando dois elevadores de 7 andares, onde o elevador que chegará será o mais próximo do andar que o mesmo foi chamado. Posso dar mais informações do projeto de forma privada.

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    Olá Nilson E., eu vi seu perfil e gostaria de lhe oferecer meu projeto, preciso que seja feito um código Verilog simulando dois elevadores de 7 andares, onde o elevador que chegará será o mais próximo do andar que o mesmo foi chamado. Posso dar mais informações do projeto de forma privada.

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    Criar um processador em verilog, contendo as especificações citadas no pdf.

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    O freelancer deverá conhecer as linguagens = C / vhdl / verilog e já ter trabalhado com FPGA / ASIC Portar e otimizar um código que já tenho pronto em "c" para vhdl ou verilog esse código gera uma string de 14 / 15 dígitos, será usado uma placa fpga xillinx spartan 6 ( a empresa xillinx disponibiliza todo o ambiente necessário ). converter a string em Sha256 usando placa asic depois de convertido em sha256 compara com um sha256 informado no inicio do processo, se igual finaliza, se não reinicia o processo. Deverá ser usado a Raspberry Pi 3 para termos uma interface ( teclado e monitor ) para inserir o código inicial

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    Implementar um jogo em verilog ou vhdl em vga

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    Jogo VGA em Verilog para FPGA

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    VHDL/verilog Encerrado left

    Segue trabalho em anexo

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    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

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    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

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    Olá Pedro, Você trabalho com FPGA (Zedboard) Xilinx? Preciso de um programa capaz de exibir a camera do Kinect em uma placa Zedboard.

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    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três estágios acessam componentes críticos de hardware: o CDB, as estações de reserva (nas quais ocorrem as renomeações) e as unidades funcionais. Você deverá implementar: (1) as estações de reserva, (2) os estágios do algoritmo, (3) as unidades funcionais de multiplicação/divisão e soma/subtração, (4...

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    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são usados para controlar LEDs que utilizem drives LPD6803, WS2801, etc. O software envia os dados (frames) através de pacote UDP para o hardware (FPGA) que recebe, armazena em buffer de memoria RAM do FPGA e então envia estes dados para os LEDs através de uma porta SPI que deve ser implementada dentro do FPGA. Monitorando e capturando os pacotes UDP que o computador...

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    I need to implement a complete FPGA system using Verilog in Vivado Design Suite. Professional FPGA experts are required. Please find the details of the project in the attachment.

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    Required the verilog implementation of N bit Montgomery Radix 8 bit multiplier and for addition use the CLA adder.

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    Using Pynq Z2 FPGA to connect a camera (OV7670 - CMOS Sensor), and then display the video on a monitor through HDMI output. The Project is built using VHDL language and IP blocks. The purpose of this it's to build also nurual network to recognize a face/person so the camera can follow the object using servo motor.

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    Hello, I'm hiring a dev who's very hot with FGPA. Need him to create cryptocurrency miner/blockchain. Specificly Xilinx Alveo U200 & U250 Cards. I can pay a lot. Contact me I'm very active. #FPGA - #XILINX #ALVEO #ALVEOu200 #ALVEOu250 #XRT #MINING #CRYPTO #DEVELOPPER #FREELANCER #FREELANCE

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    Verilog FPGA Code implementation of FEC RS(198, 194) decoder.

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    I want go get help to implement FEC RS(198, 194)

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    ASIC designer -- 2 Encerrado left

    One of the most prestigious companies in the field of ASIC Design is looking for a talented Digital ASIC Designer. Previous work with SOC & Synopsys Design Compiler is an asset. The currently defined project is designing a miner chip (ASIC miner) based on the SHA-256 algorithm with the aim of reducing power consumption and improving speed. Send me a message if interested. Looking forward to your resume

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    I have launched a crypto Mining company and would like building a business plan along with financials & multiple stages. GPU & ASIC Mining Facility with a website selling capacity. i am looking for an experienced Crypto Mining business plan writer who understands the BTC Network and halving. and how to price model out finances on BTC Miners along with other miners & GPU based farms Ideally someone who can Scope and fixed fee per section but it's going to be ongoing work and updates needed as markets change

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    5G RAN FPGA Design Encerrado left

    ...have an internal project for 5G RAN FPGA design for DFE products: Skills: Job Description- Senior MTS RTL design 5G Product( 2 positions) · Candidate must have at least Bachelors or Masters EE - FPGA design experience (RTL Coding, comms, DFE(DPD, DUC, DDC, FFT, FIR, CFR) · Candidate must have verifiable experience for a minimum 6 years as a Verilog/System Verilog/ VHDL/RTL programmer with extensive Verification test bench development experience · Preferred prior project experience in 5G ORAN - RU/DU. DSP knowledge Matlab modeling is preferred. · eCPRI experience preferred . Special consideration will be given to those who have experience as 100G Ethernet or 10G Ethernet , IEEE 1588 · Knowledge of Queuing theory &mid...

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    I want you to desgin an IC chip description document. I need you to understand the verilog design and create some design descriotions, describing its fucntions in detail. The chip design has 3 main blocks ADC, PMU and sensors. These 3 blocks contain the most important functions of this chip. Please bid if you are experienced in wrting technical design documents for chip desing in detail. Thanks!

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    FPGA Packets Delay Encerrado left

    The project consists in implementing a buffer delay on a 100G traffic done in an Xilinx Alveo FPGA

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    I need to design a Hilbert transform and test it in Matlab before implementing it on FPGA. I have never created a Hilbert transform with Matlab without the hilbert() function, and the function does not return coefficients. I can't find the documentation on how to do it. I need someone to help with it. The Matlab code must also use the filter on sample data and return complex values after the transform. You should provide the Matlab code used to create the filter and get the coefficients. I will pay $70 USD for the task.

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    Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    Lattice FPGA project Encerrado left

    Hello, I need a Lattice FPGA specialist to review my simple LCMX02 Lattice PLD design. I can not make it work, and some help is needed to understand why the PLD does not respond to the JTAG file. This is a very specific project, specifically for Lattice FPGA. I designed with other types of FPGA, and got stuck when I switched to Lattice family of parts. Thank you!

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    I have the code for I2C slave. I want help in writing the verilog code for I2C Master testbench to communicate with the given slave. It can send a few i2C write and read commands (with address, data, etc). I have attached the code for I2C slave alonside for your reference.

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    code for SPI master to send data to a GPU. project setup for the customer's terasic FPGA board. assignment. demonstration of contents via zoom meeting. I will try to complete the project before the specified end date.

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    Hi Islam Muhammad S., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    Hi Islam Muhammad S., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    Simulation Encerrado left

    Vlsi project implementation of IIR FILTER

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    Creating 2-chain Arbiter PUF on specific FPGA with 64-stages MUX for each chain. The output response PUF will be sent to external device, i.e. Arduino (microcontroller). On the other words, the output response PUF will be processed further on Arduino/microcontroller device

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    Your job is to write verilog code for i2c communication and interface it with a processor. Take data from the slave through the accelerator and store it in a memory. Make the processor read the data from that memory and give its response. Now write that response data back to the slave.

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    SOC Verification Encerrado left

    Experience: 6-7 years Job Description: 1. Experience in ASIC verification, preferably baseband/ controller side 2. Experience in Industry standard protocols ARM Interconnects(AHB, APB), SPI, UART, I2C, DMA, Serial Flash, Security and Encryption. 3. Full chip SoC (C and SV based), Subsystem and Block/IP level verification. Test Bench generation with ability to run embedded C programs. Must have experience of 2-3 SoC verification. 4. Experience in HDL(Verilog, VHDL) and HVL(System Verilog, Specman) based functional verification. Experience in code coverage. 5. Experience in Verification methodologies(UVM, OVM and eRM). language simulation (Verilog-AMS, SystemVerilog). 7. Experience in Mentor, Cadence and Synopsys simulators. 8. Build automated Test bench and reg...

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    We are a Registered Training Organisation (RTO) We have one Dual Diploma on scope We have been trading since January 2022 (very recent) and our first intake of students was in March 2022. We only managed to get 6 students enrolled! This ...services. Is it possible you can give us a quote on this first year Audit please taking into consideration that we had only 6 students starting Mch 2022. The Audit of the financials requires Signed Auditors Independence Declaration Independent Auditor's Report A Copy of the Certificate of Public Practice certificate of the person conducting the audit Details of the auditors registration with ASIC NOTE: once i submit our application to the government it can take 10 months to be approved (or longer) hence there is an urgency to this audi...

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    I need Verilog code for Energy-Efficient Logarithmic Square Rooter. It should be done within 1-2 days maximum.

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    ASIC designer Encerrado left

    One of the most prestigious companies in the field of ASIC Design is looking for a talented Digital ASIC Designer. Previous work with SOC & Synopsys Design Compiler is an asset. The currently defined project is designing a miner chip (ASIC miner) based on the SHA-256 algorithm with the aim of reducing power consumption and improving speed. Send me a message if interested. Looking forward to your resume

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    It is required to generate arbitrary signals in FPGA for Real Time Controls using Servo Proportional Valve with Control signals of ( +/- 10 VDC ). The various types of other signal generation in FPGA besides Arbitrary signal can be Square, Sine, Triangular. Generation of white noise signal for Real time control is also required.

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    Need help with code and set up for SPI protocol to send data from an FPGA to a GPU, explain code/software procedure and wiring. can forward technical specs for both devices to be used

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    I am looking to develop a Verification Code using System Verilog for USB 2.0 Protocol and also I want a verification plan for that . Kindly note that I want Complete TB code for all the components in Environment and also Test and Top instances as well . For any query/ or clarity ping me.

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    Hi Islam Muhammad S., I noticed your profile and would like to offer you my project.

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    A complete color sorter Machine Firmware needs to be converted into Intel Quartus Project, The project contains IP Cores as well as softcore processor and the verilog coding part, All these to be integrated as a single bit file and to be implemented it on a Cyclone V FPGA Board.

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    Hi. Attached a few spike from scope capture. Need at least 8 channels simultaniously. 1. how to get detect these with a precision of 1mV? 2. how to get the value in stm32? (worked with these a lot) (or do we need an fpga) Freq is 200hz at first. Looking to get to 1 khz in the near future. Duration of the spike is only 5 to 12 microseconds. What is the best way to do this precisely ? heard tons of ideas (peak-detect circuit, 20 msps adc, etc ) , but need real proven experience. !!! please apply only if done this succefully. In the opening bid propose direclty your solution. Biggest bids will be disqualified. Stop bidding the top of freelancers brackets. No B*****S approach. Will be paid only if it WORKS! Need STM32 code, parts id, and pcb design.

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    I have attached the details below

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