(SystemVerilog) "Memory model / byte rotation" and "Two sub-problems for the SHA-1 algorithm"
$10-30 USD
Cancelado
Publicado há quase 7 anos
$10-30 USD
Pago na entrega
Must know SystemVerilog coding
2 parts
First Part
Suppose each memory word is 32-bits, comprising of 4 bytes.
• Write back to memory with each memory word left-rotated by one
byte.
• Example (word shown in hexadecimal):
M[0] = 32’h01234567
M[1] = 32’h02468ace
Each “hexadecimal” digit is 4 bits. e.g., “67” means “0110_0111”
(8 bits)
• Write back to memory with “most significant byte” left-rotated to
the “least significant byte” position.
M[100] = 32’h23456701
M[111] = 32’h468ace02
Second part is Secure Hash Algorithm
Will provide more documents and information to whoever I give the project to
How long will it take you to finish the job?
3 days.
Proposal:
Hello! I am an experienced Engineer and have been helping out many on this platform. It would be great if I could help you out. Thank you!
I have been working as a SystemVerilog/verilog professional since last 2 year in a reputed service company. I have been mainly working in DFT domain but earlier I worked for a verification project. There I had to deal with SystemVerilog. I am interested to work in this project.!