SiC AFE Converter Hardware Design

I’m building a 3-phase, SiC-based Active Front End to feed the 650 Vdc bus of our 5 HP axial-flux PMSM test rig. The topology will use Infineon IMW120R030M1H (or an equivalent 1200 V device) switching from a 415 V, 50 Hz grid. The grid-side filter is the part I consider most critical, so I’ll look closely at your approach to sizing and damping an L or LCL stage that keeps THDi and ripple comfortably inside IEC limits while maintaining good dynamic response. What I need from you • Full schematic in Altium Designer, including:  – SiC power stage, isolated gate drivers with UVLO and Miller clamp  – Comprehensive over-current and over-voltage protection  – Calculated L/LCL filter network with component stress analysis • Complete, order-ready BOM with alternative part choices for long-lead items • Design notes and equations that justify component ratings and magnetic selections • One round of PCB layout review focused on high-frequency loop integrity, creepage/clearance and EMI considerations I’ll provide system-level requirements, mechanical constraints and any measured motor data you need. Highlight relevant experience with SiC AFEs, grid-connected converters or high-efficiency motor drives when you reply; that’s the main criterion I’ll use to shortlist candidates. REQUIRED EXPERIENCE: - Minimum 4 years hands-on experience designing SiC or IGBT-based power converters (VFDs, solar inverters, or motor drives) - Demonstrated experience with gate driver isolation design for 600V+ systems - Familiarity with Voltage Oriented Control (VOC) architecture for grid-tie converters - Experience with TI C2000 (F28379D or similar) is a strong plus - Must be comfortable working from a datasheet and providing design calculations (not just reference copying) DELIVERABLES: - Complete schematic (Altium/OrCAD project files) - Design calculation document (gate driver sizing, protection thresholds, filter design with justification) - Bill of materials with sourcing links - Review support during PCB layout phase HOW TO APPLY — Please answer these in your proposal: 1. Describe one SiC-based converter project you've designed, including DC bus voltage and switching frequency used 2. How would you size a gate driver for a 1200V SiC MOSFET switching at 50kHz? 3. What is your approach to anti-islanding protection for a grid-tie regenerative converter? (or state if scope excludes true regen, braking-resistor only) NDA will be required before detailed motor specifications are shared. Screening filter: Reject anyone who can't answer Q2 with actual numbers (Qg, switching loss curves, gate resistor selection) — this filters out people who've only worked with off-the-shelf VFD modules. Posting 2 — Embedded Firmware Engineer (TI C2000, Sensorless FOC) Title: TI C2000 Firmware Engineer — Sensorless FOC for PMSM Motor Drive Category: Embedded Systems / Firmware Development Budget type: Hourly recommended (₹900–1,500/hour, $11–18/hour) Description: We need an embedded firmware engineer to implement Field Oriented Control (FOC) and Voltage Oriented Control (VOC) algorithms on a TI C2000 microcontroller (F28379D, dual-core) for a custom motor drive controller. SCOPE OF WORK: - Port Simulink-validated FOC algorithm (Clarke/Park transforms, PI current/speed loops, SVPWM) to C2000 firmware - Implement sensorless back-EMF Luenberger observer for rotor position/speed estimation (motor has very low native inductance ~27.5µH, external phase inductors used — observer tuning experience with low-inductance motors is valuable) - Implement I-f open-loop startup below ~150 RPM, handover to closed-loop observer above threshold - Implement Voltage Oriented Control (VOC) for grid-side AFE including PLL for grid synchronization - Configure ePWM/HRTIM peripherals for SVPWM generation at 50kHz - Implement protection logic: overcurrent trip, overvoltage trip, thermal shutdown - Implement Modbus RTU communication over RS485 - Code optimization to fit within PWM period execution budget REQUIRED EXPERIENCE: - Minimum 3 years firmware development on TI C2000 (F28xxx series) - Demonstrated experience implementing FOC for PMSM or BLDC motors - Experience with sensorless (back-EMF based) position estimation — NOT just encoder-based control - Fixed-point or IQ-math experience on C2000 - Familiarity with TI MotorWare or InstaSPIN libraries is a strong plus - Experience with Simulink-to-C code generation (Embedded Coder) is a plus but not mandatory DELIVERABLES: - Complete, documented C firmware source code (full ownership transferred, no compiled-binary-only delivery) - Code architecture documentation - Tuning report for observer gains and PI controller parameters - Support during hardware bring-up and debug phase HOW TO APPLY — Please answer these in your proposal: 1. Describe a sensorless FOC project you've implemented — what observer type did you use (Luenberger, sliding mode, EKF) and what was the minimum reliable operating speed? 2. How do you handle dead-time compensation in your SVPWM implementation? 3. Have you worked with motors with unusually low stator inductance (<100µH)? What challenges did that create for sensorless control? NDA required before motor datasheet and full architecture are shared. Screening filter: Reject anyone who only mentions encoder-based FOC experience without sensorless — that's a fundamentally different (and easier) problem. Posting 3 — PCB Layout Engineer (High-Voltage SiC Power Electronics) Title: PCB Layout Engineer — High-Voltage SiC Power Converter (650V, 50kHz Switching) Category: PCB Design / Electrical Engineering Budget type: Fixed price per board (recommend ₹80,000–150,000 per board, 3 boards total) Description: We need an experienced PCB layout engineer to lay out 3 boards for a custom motor drive controller: 1. AFE (Active Front End) power board — SiC switches, 650V DC bus 2. Motor drive inverter board — SiC switches, FOC control interface 3. Low-voltage control + communication board — TI C2000, RS485, SMPS REQUIRED EXPERIENCE: - Minimum 3 years PCB layout experience for power electronics, specifically SiC or fast-switching IGBT designs - Demonstrated understanding of: - Minimizing parasitic inductance in switching loops - High-voltage creepage/clearance design (650V DC, safety margins) - Thermal via stitching for power device heat dissipation - Gate driver trace length matching for dead-time accuracy - EMI-conscious layout (ground plane strategy, filter placement) - Experience with Altium Designer (preferred) or OrCAD - Experience laying out isolated gate driver circuits and isolated sensing circuits (current/voltage sensors) DELIVERABLES: - Complete PCB layout files (Altium project, Gerbers, drill files) - 3D model/render for mechanical fit verification - Design rule check (DRC) report - Brief design rationale document (why specific layout choices were made for high-frequency switching sections) HOW TO APPLY — Please share: 1. Portfolio examples of power electronics PCB layouts you've completed (especially anything with SiC/fast switching, 600V+ designs) 2. Your approach to minimizing switching loop inductance for a SiC half-bridge 3. Your experience with creepage/clearance requirements for 650V isolated systems (per IEC 60664 or similar standard) NDA required before detailed schematics are shared.

Project ID: 40527353