Designing a fully-differential Miller compensated two-stage opamp with CMFB.

Goal You are tasked with designing a fully-differential Miller compensated two-stage opamp with CMFB. This opamp will be eventually used to form an inverting amplifier with a gain of −2, with the resistors R1 = 100kΩ and R2 = 200kΩ. Check Table I to find out the values of RL andCL. Draw the block-level schematic diagram of the closed-loop amplifier with the load. Break the loop at the input of the the first-stage, and calculate the loop gain for your theoretical calculations. The opamp must be designed such that a) The dc loop gain must be greater than 60dB. b) The closed-loop 3-dB bandwidth must not be smaller than 1MHz. The differential mode phase margin must be such that the closed-loop frequency response does not exhibit any peaking in its magnitude response. c) All the CMFB loops must have a phase-margin of at least 60 degrees. The UGB of the CMFB loops must be at least 1/4th the UGB of the differential loop. d) You are free to choose any appropriate CMFB variant for each stage that satisfies the below conditions. (a) The output common-mode of the second stage must be set toVcm =Vdd/2. (b) You cannot use any resistor greater than 1MΩ in any CMFB. For designing the OTA, you are given the following ideal components: Two ideal voltage sources: one with the value Vdd and another with the value Vcm = Vdd/2, an ideal ground, a refer ence current source of 1µA for biasing. All the other bias voltages/currents need to be derived from these. The load can be modeled using an ideal resistor and a capacitor. You can also use ideal resistors and capacitors for compensating both the differential loop. You can use ideal resistors and capacitors for the common-mode feedback (CMFB) loop RL= 20kΩ , CL=1pF Use the nMOS and pMOS transistors, from the “180nm generic process design kit” (gpdk180 library) in Cadence. It should be available by default in all your virtualbox installations.– The minimum length is 180nm for the process and the nominal supply voltage is Vdd = 1.8V. No negative supplies allowed.– Forall the nMOS transistors the body terminal has to be connected to the ground, while for the pMOS it could be connected to the corresponding source terminal.

ID do Projeto: 39980770