Low power design has attracted tremendous attention in recent years. It reduces the packaging and cooling costs as well as prolong the life span of integrated circuits . Digital signal processing (DSP) is one of the fastest growing fields of technology in the world, with very great high rate. New DSP applications results from advances in digital filtering.
The field of Digital filtering is divided into Finite duration Impulse Response (FIR) filters and Infinite duration Impulse Response (IIR) filters. FIR filters have two important advantages over IIR filters. First, they are guaranteed to be stable, even the filter coefficients have been quantized. Second, they may be constrained to have linear phase .A FIR filter also have less round of noises because of its non-recursive realization.
In this project we implement FIR filter using enhanced row bypassing multiplier. The Idea of power saving is to eliminate unnecessary computation via signal bypassing. To achieve high execution speed, parallel array multipliers are used in FIR filters. But these multipliers consume high amount of power in DSP computations, and thus power efficient multipliers are very important for the design of low power DSP systems. The implementation of this FIR filter is done by using VHDL, Synthesized by using Xilinx synthesis.