Design an FSM that has an input X and an output Y . Whenever X changes from 0 to 1, Y should become 1
for two clock cycles and then return to 0 – even if X is still 1.
2. Design an FSM with no inputs and three outputs x, y, and z. The bit sequence x yz should always cycle
through the following value: 000, 001, 010, 100, (repeat)
I only need to write one Verilog file containing both the module
and the testbench for the FSM for two parts.