Efficient Multiplier Design via Cadence Virtuoso

₹1500-12500 INR

Closed

Posted about 1 month ago

₹1500-12500 INR

Paid on delivery

Low Power, High Speed,Area Efficient Multiplier based on the PTL logic style is the project title.I have to implement using cadence virtuoso gpdk090 nm technology and I want improvement of this paper for paper publishment.

Electrical Engineering

Electronics

Engineering

Project ID: 40376041

About the project

4 proposals

Remote project

Active 22 secs ago

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4 freelancers are bidding on average ₹9,500 INR for this job

@riab54

I have a dedicated analog design team with strong hands-on experience in Cadence Virtuoso, specializing in low-power and high-speed circuit design. Your project aligns well with our expertise, and we are confident in delivering an efficient multiplier design with proper schematic, simulation, and layout validation. If you’re looking for a reliable and technically sound execution, let’s connect over chat to discuss your exact requirements and timeline.

₹11,000 INR in 12 days

5.0

(2 reviews)

3.6

@AbdulSammiKhan

I will do this project in no time. You will be satisfied with the work and performance and you will have the project ready in no time. Thank you so much

₹14,500 INR in 7 days

0.0

(0 reviews)

0.0

@harshadg39

mplementing a Low Power, High Speed, and Area Efficient Multiplier in Cadence Virtuoso using gpdk 90nm is a solid project, but to get it published in a reputable journal (like IEEE Access or Springer), you must move beyond simple implementation and offer a novel contribution.

₹5,500 INR in 7 days