I need either a brand new implementation for a BPF FIR filter, or an improvement to the one already uploaded.
For improvements to the uploaded code:
- a handshaking FSM system between the FILTER and the ROM input signal generator
- the filter block should be divided into more modules with better use of multipliers and adders. Also, it's coefficients should not be hardcoded, they should be read from a .COE file
- The Xilinx project should be divided into 3 main parts:
-- Filter part
-- Software Simulation part (with the Input Chirp)
-- Hardware Verification part (Using Chipscope)
- Software to be used: Modelsim 10.1 SE (for an analog view of the signal), and Xilinx ISE Design Suite
Hi I am making this bid to know why you need improvements, is it due to poor design or you need extra features, please tell me, waiting your reply best regards
5 freelancers are bidding on average $98 for this job
My qualification is M.Tech. in VLSI and Embedded System. I have completed my project on FIR filter using verilog in xilinx tool during my curriculum.