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Advanced Verilog FIR Band Pass Filter Implementation

I need either a brand new implementation for a BPF FIR filter, or an improvement to the one already uploaded.

For improvements to the uploaded code:

- a handshaking FSM system between the FILTER and the ROM input signal generator

- the filter block should be divided into more modules with better use of multipliers and adders. Also, it's coefficients should not be hardcoded, they should be read from a .COE file

- The Xilinx project should be divided into 3 main parts:

-- Filter part

-- Software Simulation part (with the Input Chirp)

-- Hardware Verification part (Using Chipscope)

- Software to be used: Modelsim 10.1 SE (for an analog view of the signal), and Xilinx ISE Design Suite

Habilidades: Engenharia Elétrica, Eletrônica, Verilog / VHDL

Ver mais: fir filter design, xilinx, xilinx system, system verilog, Signal and system, ise, Electrical System , analog filter design, input verification code, file system simulation, xilinx project, advanced filter, fir filter code, generator parts, file system simulation code, electrical engineering system, project simulation electrical, code filter band pass, project electrical simulation, hardware generator, simulation project electrical engineering, engineering block project, verilog design, fsm using verilog, electrical project simulation

Acerca do Empregador:
( 24 comentários ) CAIRO, Egypt

ID do Projeto: #6767767

Premiar a:

ahmedmohamed85

Hi I am making this bid to know why you need improvements, is it due to poor design or you need extra features, please tell me, waiting your reply best regards

$90 USD em 3 dias
(108 Avaliações)
6.9

5 freelancers are bidding on average $98 for this job

loi09dt1

A proposal has not yet been provided

$166 USD in 3 dias
(13 Comentários)
4.3
jaydeeprangani

My qualification is M.Tech. in VLSI and Embedded System. I have completed my project on FIR filter using verilog in xilinx tool during my curriculum.

$90 USD in 3 dias
(1 Comentário)
0.0
Bordhan

i have good knowledge on DSP and verilog , worked with Modelsim 10.1 SE , and Xilinx ISE Design Suiteand I am capable of doing this.

$72 USD in 3 dias
(0 Comentários)
0.0
SANGITAR

I have proficiency in verilog and VHDL, i am ready to take on the task,pls visit [url removed, login to view] to know more about us.

$72 USD in 3 dias
(0 Comentários)
0.0