design and simulate a circuit that accepts as input two 5-bits binary numbers and shows the result of their integer product in a 3 seven-segment display in hexadecimal format. Test circuit in a FPGA Cyclone II (DE1 board), Cyclone II EP2C20F484C7. Quartus II version 12.1 or later is the software to be used. There is an auxiliary file (an Excel .csv file) which is to be included/used for the project. More info will/can be provide, if necessary, to complete the project.
Dear sir I already have the de1 board , and I will give you the complete design in 5 hours with video demonstration, I am very interested in working on your project and I am willing to negotiate for the budget