Digital Circuit will be represented and simulated via ModelSim simulator.
Consider the digital circuit represented below. Two eight-bit wide data input ports are
added. The result is then used to set one of eight output lines according to predefined
thresholds. Code this design in VHDL and verify its correctness by writing a testbench.
Simulate the design using the ModelSim simulator.
What is the difference between the data type bit and the data type std_logic in VHDL?
What is the difference between the data type bit_vector and the data type
std_logic_vector in VHDL?
What is the difference between VHDL signals and variables?
Which data types are natively present in VHDL?
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Dear sir I have more than 10 years experience in digital design using VHDL, please check my profile, also please message me so that we can discuss Best regards
For more details inbox me so that we can discuss in detail. For more details inbox me so that we can discuss in detail. For more details inbox me so that we can discuss in detail.
Bit has only 2 values '0','1' std_logic has 9 values 'U','0','1','X','Z','-','H','L','W' Bit and bit_vector are natively present in VHDL. I assume that the inputs numbers are unsigned. Is it right ?
I made many vhdl projects both at work and at university. so your project is very easy . moreover if you are student i can do this freely dont hesitate to contact with me :)