Altera CPLD SDRAM Project - Old 8bit Platform (65C02)

I am in the process of modernizing an old 8 Meg RAM, 5v card.

Review the attached files (1 pic, 1 ABLE). Pic shows current RAM card that will be used as a prototype test bed. ABLE is from the GAL.

Review datasheet for Micron MT48LC8M8A2. We are open to any 8Meg SRAM, DRAM, PSRAM that is cost effective and preferably still in production. Any bit size or voltage is allowed. Main objective is a single TSOP case and cost effective.

We are looking at an Altera MAX 7032a CPLD. We are also open to something larger if needed, or another manufacture if there is reason. However we prefer Altera since the software appears to be simpler to operate compared to others.

Once we have agreed on all parts for the project I will proceed as follows: The old PCB will be stripped of one IC at a time. The F245 (U28) will be replaced by a 74LVC245A which will provide level shifting from v5 to 3.3v. I will fly-wire in the Altera CPLD in place of each IC, one at a time to verify the coding, starting with the GAL. U29 is a LS75, U31-32 are F139, U25-26 are F04. RP1-3 will be staying, and will ultimately be added to the SDRAM address lines, as I assume this is still current practice. The DRAM will be the last thing replaced. I am very skilled with soldering and these mods will not be an issue. A MIC5319 Micrel LDO will be added for [url removed, login to view] power. A TX0108 TI can be added should we find issues with the CPLD replacing the F04s. You can advise on current best practices.

Note: Currently there is standard [url removed, login to view] CBR refresh support, however you can chose any refresh you desire for the RAM used.

You will also be responsible for all initialization support for whatever RAM is used.

Address translation will be needed from 1Meg x 4bit DRAMs to whatever RAM is used. Currently the F139s provide this. I can supply more background information of the memory bus signals if needed.

Requirement: All Verilog should be well commented and in blocks/groups which allows for easy understanding.

All testing and verification of code will be my responsibility. You will help debug code as needed. We can setup milestones if desired.

This project is about 30 days from starting. We want to first discuss parts with you before finalizing the new PCB layout.

Note: This is related to at least 2 other projects, and are almost identical. Should your work be successful we will speak with you about the other projects which will be paid for as agreed separately and NOT part of this project price. Bonus will be paid for excellent and timely work.

Please ask if there are any questions. Thanks!

Habilidades: Engenharia Elétrica, Eletrônica, Verilog / VHDL

Veja mais: translation groups, the prototype part 1, starting objective c, software testing practice, software testing best practices, prototype 3 review, practice in software testing, power translation, objective c platform, i want to be an electrical engineering, find translation memory, engineering projects needed, best practice software testing, 2 power standard, find a manufacture, soldering, reactive, prototype PCB, process wire, pcb testing

Acerca do Empregador:
( 6 comentários ) Cherry Hill, United States

ID do Projeto: #6016474

2 freelancers estão ofertando em média $489 para esse trabalho


Dear sir, I have more than 7 years experience in digital design using Altera CPLDs and FPGA's please read the reviews written on me to be sure that i can do your project perfectly

$333 USD in 15 dias
(90 Comentários)

Hi , I have extensive experience designing large applications for Altera FPGA's and CPLD . I can also do schematic capture and PCB layout for this board using Altium . Regards , Ahmed

$644 USD in 3 dias
(0 Comentários)