This is a school assignment that requires us to design a simple 5-stage pipeline CPU. It should be able to detect data hazard and insert bubbles into the pipeline accordingly.
This is the description of the assignment:
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12 freelancers estão ofertando em média $278 para este trabalho
Dear sir, I have more than 5 years experience in digital design using verilog I have already worked in similar project before please read the reviews written on me for similar CPU design project
Hi, I am a graduate in EEE.I have 15 years of experience in programming,electronic design and teaching.I can do this work for you. Thanks and Regards, Prasad.M