Cancelado

Write VHDL code for msf and dcf transmitter(detect new second & min) (detect value of transmitted bits)

we are sampling radio signals form birmingham uk and germany, the task is to write the code for a DCF_SYNC MSF_SYNC DCF_BIT AND MSF_BIT. the dcf and msf sync codes are to detect a new second (SO) and a new minute (mo) on the dcf and on the msf bits. while the bit files detects the value of the transmitted bits on the DCF and A and B bits on the MSF.

EXPLANATION IN DETAIL:

DCF SYNC:

1) the first thing to be done is to build a state machine which checks when the system in changing from low to high.

the problem here is that there is noise on the signal and i dont want the state machine to latch on to one of the noise signals.

2) so to solve this time needs to be measured(so we know each pulse gotten is after a second from the last one) by measuring the clock pulses, by counting the clock cycles. so what i need is a counter counting up with the clock. the clock frequency is 125Mhz. so here you work out the number of clock cycles in a second which is (125,000,000), and get a counter capable of counting up to that.

after the first rising edge start the counter and reset it to 0 at the first second.

the parameters for the clock cycles are 980ms < t < 1080ms. so when a low to high is detected you check whether the number of clock cycles is between that [url removed, login to view] so you find a transition within the acceptable range one second later.

ALSO at the 59th second we get a 2000ms(2 second) gap. so i need some code to recognise this code and recognise that this is the start of the new minute. you can use the parameters of 2000ms +/- 20ms for this.

A RESET, is also needed in a case where here is no second pulse after 3 seconds have passed.

MSF_SYNC:

the msf is also the same.

THE ONLY DIFFERENCE HERE IS THAT. there is no 2000ms (2 seconds) gap at the 59th second, but rather a 500ms pulse that indicates the start of a new minute. AND ALSO you need to write some code to detect the falling edge for the MSF SYNC, so the 500ms pulse can be detected.

NOTE: THAT ONE THE DCF THE GAP IS THE 59TH SECOND SO FTER THIS THERE IS THE START OF A NEW MINUTE (SECOND 0 THEN 1), BUT ON THE MSF THE 500MS PULSE IS ON THE SECOND 0 AND THE NEXT ONE IS SECOND 1. SO ON THE MSF YOU ONLY KNOW A NEW MINUTE HAS STARTED ABOUT HALFWAY THROUGH THE 500MS PULSE.

SO ON THE DCF BIT WHEN YOU RECEIVE A SIGNAL FROM THE DCF THE NEXT BIT WILL BE BIT NUMBER 0

WHILE ON THE MSF WHEN YOU RECEIVE A SIGNAL FROM THE DCF THE NEXT BIT WILL BE BIT NUMBER 1

DCF BIT:This component detects the value of the transmitted bit on the DCF signal

MSF BIT: This component detects the value of the transmitted A and B bits on the MSF signal

SO WHAT I NEED IS FOR CODES TO BE WRITTEN FOR THESE FILES, WHICH CORRESPONDS TO THE EXPLANATION I GAVE ABOVE.

TEMPLATES FOR THE FOUR FILES I WANT YOU TO WRITE THE CODES FOR ( DCF SYNC, MSF SYNC, DCF BIT, MSF BIT) ARE ALL ATTACHED. WITH MORE EXPLANATION IN THEM.

Habilidades: Eletrônica, Verilog / VHDL

Ver mais: write up templates, vhdl and verilog, one bits, min range, low bits, code radio, bits of, bit frequency, bit bits, all the bits, all bits, 1 bits, 0 bits, i second you, dcf number, write a note on get, want to write a note, get a code, write some code, vhdl, verilog vhdl, Value, system verilog, Signal and system, need to write code

Acerca do Empregador:
( 0 comentários ) United Kingdom

ID do Projeto: #5088250

8 freelancers estão ofertando em média $235 para este trabalho

ahmedmohamed85

Dear sir, i have more than 5 years experience in digital design using vhdl, I have already worked on similar project last year for sampling UK and Germany radio signals, you will be very happy with the work done

$333 USD in 15 dias
(45 Comentários)
6.2
zeshannaseer

Dear Client, I have extensive experience in VHDL/Verilog and FPGA design and development.I can do this task for you.I just need 5 days to complete task.I have 100% completion rate with VHDL/Ver Mais

$250 USD in 5 dias
(13 Comentários)
4.5
amibio

Hi, VHDL expert here with 13+ years experience. I have already implemented DCF77 and MSF receivers for UK and France-based clients. Since these long wave signals cannot be received in Greece (due to the distance), both Mais

$298 USD in 7 dias
(1 Comentário)
4.0
ForHighQuality

Ready to work with you.I can assure you of my timeliness, quality and experience. I can start work immediately.

$103 USD in 3 dias
(0 Comentários)
0.0
RAJCDAC

A proposal has not yet been provided

$309 USD in 3 dias
(0 Comentários)
0.0
pmullappilly

Hi, I am a graduate in EEE.I have 15 years of experience in programming,electronic design and teaching.I can do this work for you. Thanks and Regards, Prasad.M

$277 USD in 20 dias
(0 Comentários)
0.0
khanhln

Hi, I can do it in 1 day. But there're some things need to be clear. (1). About new bit trigger ("tr") output signal in DCF_BITS and MSF_BITS. "In addition, you have to set the tr output high for only one clock cycl Mais

$88 USD em 1 dia
(0 Comentários)
0.0
PrinceJion

i can help you. i am electronics Engineer and having couple of year experience in this field.I have worked on [url removed, login to view] video compression core and Nand Flash.

$222 USD in 7 dias
(0 Comentários)
1.7