Digital Design - VHDL Programm

Vivado 2016.1 will be used.

Create a testbench and simulate it in ModelSim with the help of the

already provided script files.

Design a synchronous system in VHDL which controls a two-storied elevator (ground floor and first floor). You will implement it with a two-process FSM as described above. The clock signal has a frequency of 10 MHz. The circuit should be initialized with a high-active reset signal. After a reset the elevator is always situated at the ground floor.

The controller has six inputs (in addition to clock and reset):

Button GF inside the cabin to descend to the ground floor (gf_cab_i).

Button F1 inside the cabin to ascend to the first floor (f1_cab_i).

Button UP located on the ground floor to call the elevator cabin (gf_call_i).

Button DOWN located on the first floor to call the elevator cabin (f1_call_i).

One sensor to determine if the cabin has reached the ground floor (gf_end_i)

Another sensor to determine if the cabin has reached the first floor (f1_end_i).

The output of the FSM controls the elevator engine (engine_o):

“10” moves the cabin down.

“00” stops the cabin.

“01” moves the cabin up.

“11” illegal state.

Draw the state diagram of the controller. (Hint: there are probably four states: GF, F1, UP,


Code the FSM in VHDL and split it into two processes as described above

What do you think will be generated out of the VHDL code you have written (DFF or

combinatorial logic?).

Compare the two versions of FSM. What do you think are the benefits of the one-process

method and of the two-process method?

Create a testbench for your design and simulate it with ModelSim

Habilidades: Design Digital, Eletrônica, Embedded Systems, FPGA, Verilog / VHDL

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Acerca do Empregador:
( 0 comentários ) Vienna, Austria

ID do Projeto: #18720968

11 freelancers estão ofertando em média €39 para esse trabalho


Dear sir I have more than 10 years experience in digital design using vhdl please check my profile also please message me so that we can discuss

€88 EUR em 1 dia
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having more than 8 yrs of industry experience in verilog and vhdl . I can do this well without any functional issues. thanks Rajagopal

€55 EUR em 1 dia
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Compare the two versions of FSM. What do you think are the benefits of the one-process method and of the two-process method? With one process all outputs are DFF so they are delayed one cycle repect to the inputs.

€50 EUR em 1 dia
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Hi there, I am interested in with this project. I'm familiar with the VHDL and Verilog design. Pls take a look in my profile. Thanks.

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Working in Digital System Designs and their programming in a federal govt department for more than 5 years. If bid is accepted, task will be completed in time and with your satisfaction. ENTITY ELEVATOR is PORT ( Mais

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Hello there, i am krishna [FPGA Engineer LogicTronix/Digitronix Nepal]. I have good expertise with VHDL programming, Digital Design and FPGA DEvelopment. I am working on this field since 5+ years professionally. Here Mais

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I have worked in digital designs especially in ALU using VHDL and have also published an article on my designs. Here is the link to my article:-[login to view URL] I will give you the Mais

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I'm an experienced FPGA engineer have expertise in RTL coding and Xilinx platforms. Im interested and willing to work in your project. Let's discuss the details

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