Cancelado

Zedboard Full-duplex UDP PL implementation in VHDL

Implement a UDP communication protocol in VHDL to transmit and receive UDP packets.

A linux based PC will send a UDP packet of arbitrary size over ethernet and zedboard FPGA should receive and do a logic operation on data and send back a packet of a different size back to the PC. Design also requires interfacing with the PHY chip on zedboard.

Important note, your implementation should ONLY use PL part of the fpga and no FPGA specific units (like cpu cores, AXI bus, HARD mac chip interface unit,...) should be used.

VHDL code should be transferable between different fpga brands, and use minimum possible amount of resources.

You will be provided a c++ code which does the mentioned test on PC side.

Habilidades: Eletrônica, FPGA, Verilog / VHDL

Veja mais: full duplex audio video flash, wavein waveout full duplex, microphone full duplex wave, the microzed chronicles, zynq pl ethernet, microzed chronicles github, zynq ethernet example, direct sound full duplex buffer, full duplex audio wavein waveout, full duplex audio player using waveinwaveout apis, tcp full duplex romana, full duplex named pipes windows, client sip full duplex symbian, fpga pci implementation vhdl, full duplex sockets, full duplex tcp connection unix, full duplex tcp socket programming, socket programming full duplex, tcp connection full duplex, win32 named pipes full duplex

Acerca do Empregador:
( 0 comentários ) Boulder, United States

ID do Projeto: #19035400

4 freelancers estão ofertando em média $313 para esse trabalho

ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Mais

$250 USD in 5 dias
(79 Comentários)
6.2
vinodluhar

Hi I have worked on FPGA implementation of various ethernet protocols like TCP UDP. I already have written a similar UDP TX Rx code in verilog. Please let me know if you have the requirement still open. We can work o Mais

$250 USD in 3 dias
(3 Comentários)
3.8
asicdsm

In the Zedboard the external PHY ( Marvell) is connected to the Ethernet MAC in PS section. It´s impossible to connect it to PL section. Your project can´t be done without an external board.

$500 USD in 7 dias
(0 Comentários)
0.0
gaihrekrishna

hello there, its krishna from LogicTronix [an FPGA Design Company]. I have worked on the TCP/IP based data transfer product design with FPGA. So interested on the project of UDP. Let me know the details!

$250 USD in 10 dias
(0 Comentários)
0.0