Implement a UDP communication protocol in VHDL to transmit and receive UDP packets.
A linux based PC will send a UDP packet of arbitrary size over ethernet and zedboard FPGA should receive and do a logic operation on data and send back a packet of a different size back to the PC. Design also requires interfacing with the PHY chip on zedboard.
Important note, your implementation should ONLY use PL part of the fpga and no FPGA specific units (like cpu cores, AXI bus, HARD mac chip interface unit,...) should be used.
VHDL code should be transferable between different fpga brands, and use minimum possible amount of resources.
You will be provided a c++ code which does the mentioned test on PC side.
4 freelancers estão ofertando em média $313 para esse trabalho
In the Zedboard the external PHY ( Marvell) is connected to the Ethernet MAC in PS section. It´s impossible to connect it to PL section. Your project can´t be done without an external board.
hello there, its krishna from LogicTronix [an FPGA Design Company]. I have worked on the TCP/IP based data transfer product design with FPGA. So interested on the project of UDP. Let me know the details!