Spartan 3 DDR-SDRAM controller / Verilog

Implement a special efficient pipelined DDR-SDRAM controller into a Spartan 3 FPGA

- Pipeline (incl. bank switching)

- Read a 64bit value

- incremet and write back the 64 bit value to the same adress

- during wait cycles on the one bank the same process should run on the other bank (alternating)

- total 4 independant DDR-SDRAMs connected to the Spartan3

- SDRAM type: V58C2512164SAJ-5

- Spartan3: XC3S1500FG676

- speed: DDR SDRAM clock min 96 MHz, no "NOP" cycles in access

- hardware already available

We provide UCF-file and Verilog interfaces to our logic.

If necessary we can provide an evaluation hardware.

Expected deliverals:

Xilinx ISE 9.1 project including well-documented Verilog sources and simulation

We will check for proper operation.

See a detailed project description attached.

Habilidades: Eletrônica, Engenharia

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Acerca do Empregador:
( 1 comentário ) Flintsbach, Germany

ID do Projeto: #150901

5 freelancers are bidding on average $1080 for this job


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$1500 USD in 21 dias
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$1100 USD in 20 dias
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$1200 USD in 20 dias
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$1100 USD in 20 dias
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$500 USD in 25 dias
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