I have a design that needs verilog code written to act as a JTAG TAP Master. It gets commands and data from another chip and needs to output JTAG commands. This all needs to fit into a 64 macrocell CPLD.
This project will be worked on together as I will provide logic traces and you will program the verilog so the jtag signal closely matches the logic traces.
I wish for someone to be in Northamerica so the time-zones are close enough for real-time communications. Please send me a PM if you are interested and I will post the logic traces for you to examine.
This project is VERY SIMPLE (how complex can you get with 64 macrocells =D)