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Digital System Design / Verilog Undergraduate Level Homework

I am currently taking an undergraduate digtal systems design class and need some help doing a homework problem. This should be easy for anybody with basic HDL experience, or computer engineering graduates.

I have attached the scanned pages from our text book which contain the question that I need completed, which is question 16.

I have also attached an electronic version our textbook. Please look at chapter 7.3. It describes an RISC processor and shows the code. You can use this code to help you with this assignment. Note that the textbook is in the .djvu format. If you are unfamiliar with this file type, please visit <[url removed, login to view]> to download a browser plugin to view this type of file.

To complete question 16, you need to write the verilog code and simulate it using Modelsim or any other circuit simulator to verify the code.

You'll need to submit the complete code and the simulator results (waveform).

These are undergraduate level stuff, so you should find them pretty easy, but If you need explanations or help, you can ask me

## Deliverables

1) All deliverables will be considered "work made for hire" under U.S. Copyright law. Employer will receive exclusive and complete copyrights to all work purchased. (No 3rd party components unless all copyright ramifications are explained AND AGREED TO by the employer on the site per the worker's Worker Legal Agreement).

For question 16 in the attached file, you need to provide:

1) Verilog code, along with detailed comments.

2) The simulator results along with waveforms. Also I need to know which simulator you are using. I prefer that you use Modelsim.

3) Instructions on how I can install a simulator and run the code myself to see the simulator results.

## Platform


Habilidades: Engenharia, Arquitetura de software, Teste de Software

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