Design of MIPS Datapath components Using Logisim

Course: Computer Organization and Architecture Project: Design of MIPS Datapath components Using Logisim Objectives After completing this project you will: · Design a 32x 32 bit register file · Design a 32 bit arithmetic and logic unit (ALU) Register File The register file consists of 32 x 32-bit registers and has the following interface as shown in Figure 1: _ BusA and BusB: 32-bit output busses for reading 2 registers _ BusW: 32-bit input bus for writing a register when RegWrite is 1 _ RA selects register to be read on BusA _ RB selects register to be read on BusB _ RW selects the register to be written