In the class account I have included the user guide for the Xilinx MMCM. For your class project you will write VHDL code to implement a circuit that will create .5X, 2X, 3X and 4X clock signals. The input to your circuit is the signal CLK_IN_100, a 100 MHz clock signal. The output signals to your circuit are CLK_OUT_50, CLK_OUT_100, CLK_OUT_200, CLK_OUT_300, and CLK_OUT_400. These should be synchronized clock outputs with frequencies 50MHz, 100MHz, 200MHz, 300MHz, and 400MHz respectively. You will use the built in MMCM component to implement your clocks. To create the different output frequencies, you will set the proper generics (see your labs for examples) for the five different output clock signals.
By midnight, 5 December email me your vhdl file. The name of the file should be CLOCK_CKT.vhd. You should email that file, and that file only. At the top (first line) of that file you should include (in comments so the code will compile) your full name and university ID.