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FFT implementation on spartan 3e

design a real time fft core using vhdl for 1024 point 16-bit radix 4 algorithm and implement on spartan 3E starter kit. the input to fft will be a image and output is to be display on the monitor.

Habilidades: FPGA, Verilog / VHDL

Ver mais: spartan, fft, spartan fft, display monitor vhdl, input type file accept image capture camera capture, fft using, radix fft butterfly verilog, vhdl display monitor, spartan starter kit serial port, spartan starter kit serial verilog code, spartan starter kit verilog, spartan starter kit, algorithm implementation, spartan starter kit analog converter vhdl, implementation spartan, input list positive number array output results, spartan starter kit simulink, vhdl spartan, vhdl implementation, 3e, input output gui display

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( 0 comentários ) Latur, India

ID do Projeto: #6812067

1 freelancer is bidding on average ₹15000 for this job

loi09dt1

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₹15000 INR in 15 dias
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