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Distributed logic simulator with graphical front-end

Description

We have written a compiler that translates source code in a parallel language into logic equations suitable for loading in to a Field-Programmable Gate Array (FPGA). The nature of the source language is that separate processes could be compiled independently. These could then be run on separate FPGAs. I now need a simulator that can display the behaviour of each part of the circuit. I expect that this program will be written in Java and will use graphics to display the waveforms of the signals being monitored. We are using a number of tools to assist us, for instance the SableCC parser-generator. This might be useful in this project, too.

References

1. The CPA2004 and PDPTA2005 papers at [url removed, login to view]

2. SableCC docs at [url removed, login to view]

pls send in samples, so i can decide the most suitable provider for this project. ANY BID WITHOUT A SAMPLE WILL BE IGNORED. There would also be mre projects after this one.

Habilidades: Redação Publicitária, Processamento de Dados, Java, Segurança na rede, Design de Sites

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Acerca do Empregador:
( 0 comentários ) port harcourt, Nigeria

ID do Projeto: #164886