ARM pseudo code and cache simulator

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you will use a cache simulator to analyze the performance (hit rate) of three cache designs. You will do this in an analysis paper which should answer the following questions:

How does the performance of a cache change with its associativity? (e.g. direct mapped vs n-way associative vs fully associative)

How does the performance of a cache change with cache size?

How does the performance change with replacement policy?

How does the performance change with the line size?

Important Information

The format of the memory trace file is the following:

The first field is “l” or “s” depending on whether the processor is loading from or storing to memory. You don't need to do anything differently for load or store.

The second field is a 32-bit memory address.

The third field is the number of bytes being requested.

You don't need to do anything with the number of bytes being requested. The only field you care about is the address. You may assume that each request will be contained in one block.

Comparing results is welcomed and encouraged.

Items to Examine

Parameters

Number of bytes in the cache (a positive power of 2)

Number of blocks in each set (associativity)

Number of bytes in a block (a positive power of 2, must be at least 4)

1 set of n blocks is fully associative

n sets of 1 block is direct mapped

n sets of m blocks is m-way set associative

Replacement policy (for caches that aren't direct mapped)

Least recently used (LRU)

First in, first out (FIFO)

Examine effect of changing cache type

Direct mapped vs. Set associative vs. Fully associative

Examine effect of replacement type

Examine effect of cache size

Examine the effect of line/block size

Write a paper with your analysis of cache designs.

Sections to Include

Introduction

Describe the purpose of the analysis. What is the goal of your analysis? What are you analyzing?

Description of Tests

What were the parameters for each test? Include the values of parameters: cache size, block size, associativity, replacement strategy.

Make sure to specify the associativity for set associative.

Why did you choose these parameter values?

Results

What were the hit rates for the different configurations?

Create plots to show your results.

x-y plot of hit rate vs cache size, with separate lines for FIFO and LRU

x-y plot of hit rate vs block size, with separate lines for FIFO and LRU

Make sure your plots are labeled on the x and y axes. y axis should be hit rate, x axis is independent variable. Give units on the independent variable (e.g. bytes)

Conclusions

How does cache design (direct mapped/set associative/fully associative) affect hit rate?

How does hit rate change with the two replacement policies?

How does cache size affect hit rate?

How does line/block size affect hit rate?

You must submit the following:

A screen capture (.mov or .mp4) showing a sample run. Your name must appear somewhere in the video. Sound is not necessary.

Your analysis paper.

Java Programação C++ Programação C Algoritmo Arquitetura de software

ID do Projeto: #37972544

Sobre o projeto

25 propostas Projeto remoto Ativo em semana passada

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