ECG Denoising Project

An electrocardiogram (ECG) device monitors the cardiac status of a patient by measuring the

electrical activity of the heart over time captured and externally recorded by skin electrodes.

These devices play a very important role to save lives of patients who survive heart attack or

suffer from serious heart diseases. The time to respond to a heart attack is very critical for these

patients. An early detection of conditions that lead to the onset of cardiac arrest allows doctors to

provide proper treatment on time and prevents death or disability from cardiac arrest.

Like any other measurement system, there are different sources of noise that contaminate the

ECG signal: the baseline wander noise (BW), electromyographic interference (EMG), and the

power line interference. The BW is induced by electrodes’ changes due to perspiration,

movement and respiration, and is typically below 0.5 Hz. The power line interference is either 50

Hz or 60 Hz and its harmonics are a significant source of noise. The baseline wandering and the

power line interference (Hum noise) are the most substantial noise and can strongly affect ECG

signal analysis. Other than these two noise elements, the remaining noise is wideband and

usually complex stochastic processes which also distort the ECG signal and affect the analysis.

One of the important phases of ECG signal processing is noise reduction in digital domain. Noise

reduction alleviates the other main processing steps such as feature extraction and classification.

Noise reduction can be performed using various filters. The goal of this project is to design a

denoising filter to attenuate the high frequency and power line interference. Figure 1 depicts a big

picture of ECG signal denoising

Habilidades: Matlab and Mathematica, Verilog / VHDL

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Acerca do Empregador:
( 0 comentários ) hyderabad, India

ID do Projeto: #6818356

2 freelancers estão ofertando em média ₹10355 para este trabalho


Dear sir, I have more than 7 years experience in digital design using VHDL and verilog, i fully understand the project and i will deliver the files today

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