1) Find the Optimal number of pipeline stages k^* by maximizing the performance/cost ratio (PCR).You are allowed to insert one delay stage into the pipeline to make latency of 1 permissible in the shortest Greedy cycle. The purpose is to yield a new reservation table leading to an optimal latency equal to the lower bound. A) Show the modified reservation table with five rows and seven columns. B) Draw the new state transition diagram for obtaining the optimal cycle. C) List all the simple cycles and greedy cycles from the state diagram. D) Prove that the new MAL equals the lower bound. E) What is the optimal throoughput of this pipeline? 2)Given a circuit with three initial inputs X, Y, Z. The outputs are the complement of the three initial inputs X', Y', Z'. Draw this circuit using any number of AND and OR gates, YOU can use ONLY two Inverters to complete the diagram.
1) I reguire the full worked out examples for question 1. 2) I require the drawn out diagram for question 2, could be in basic shapes or designs, or even a worded answer and I will draw it myslef from the instructions.