We have developed a new board that has a Spartan IIE, part number XC2S150-5.
We just want to prove that all of our interfaces are working, so we want a very simple FPGA program developed that is going to be a loop test. The project is as follows:
27Mhz clock on pin 77
AND pin 57,58,59 when all are low it is a latch state read data
in from the following pins need to stretch this pulse known as a pulse
stretcher stretched pulse is now ASI_TX_ENA_N PIN 71
49 DOWN TO 42 49=D7 48=D6 AND SO ON
ASI_TX_ENA_N PIN 71
Q7 TO Q0 Q7=70,Q6=69,Q5=68,Q4=67,Q3=63,Q2=62,Q1=61,Q0=60
simply receive it in and send it out put all other pins asleep
Once we have the board running, there will be future FPGA work requests that will be posted here for bids, so the person that successfully completes this small job will have an inside track on future work with us.
1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done.
2) Exclusive and complete copyrights to all work purchased. (No GPL, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site).
Spartan IIE, part number XC2S150-5.