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VHDL Design Assignment

A serial data line sends information in **packets of data**. Each packet comprises of a **header segment** followed by **message segment**. When a data packet is not presenton the line it is held low representing a continuous stream of zeros. A clock signal is sent with the data to give bit synch and is valid on a rising edge and the reset is active high.

## Deliverables

A serial data line sends information in **packets of data**. Each packet comprises of a **header segment** followed by **message segment**. When a data packet is not presenton the line it is held low representing a continuous stream of zeros. A clock signal is sent with the data to give bit synch and is valid on a rising edge and the reset is active high.

***Header segment:***

Ten bits long- sub divided into two fields:-

- **Start bits ** -Two bits- "11"

- **Header code** - Eight bits- "11001101"

***Message segment:***

Message data -24 bits as six BCD digits each in range 0 to 9

***_Task:

_***Design a prototype detector as a Top Level VHDL based description that will analyse the data stream. The output "Header" will go high when a valid header segment is detected and remain high until the endof the packet is reached. "Checksum" will initially be set to zero, but will then output a 4-bit checksum value formulated from the message segment based on an add and shift operation of each BCD digit received. The output "Message" will go high to indicate a checksum has been generated and will remain high until a new packet is received. Must be compiled and run on a xilinx Foundation/Webpack and as an environment the solution must be targeted at a Xilinx XCR3064XL CPLD board.

It is expected that a state machine will be used for header detection, and that the overall system will be partitioning as a number of lower level models, through the use of component instantiation. The final Top level entity must be tested and simulate by the use of of test bench entities.

## Platform

Xilinx Foundation/webpack

Habilidades: Engenharia, MySQL, PHP, Arquitetura de software, Teste de Software

Ver mais: top segment, shift bits, set bits in c, set bits, range partitioning, prototype component, number board design, low bits, line line segment, foundation design, engineering by design, detection design, component prototype, component board, component active, clock design, board prototype, bit operation, bit bits, packet design, xilinx, xilinx system, webpack, vhdl, prototype design

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