Encerrado

Verilog module hierarchy generator and parser

We are in need of a simple C# GUI tool to generate and parse Verilog module hierarchies. The software must have the following capabilities: - Represent a Verilog design in an editable graphic format, like the schematic style of a regular electric/digital/UML schematic application. In the main window, it should be possible to add new modules (graph nodes), new signals (graph edges) and modify them as in any Windows GUI application (eg drag and drop, undo and redo, etc.). A secondary window should display the hierarchy in a graphical tree. The GUI must be designed in a C# tool like Microsoft Visual .NET (Express edition is ok). A design should be loaded and saved in an XML file. - Parse a group of Verilog code design files and extract the hierarchy of modules they contain in the graphic tool, with modules as graph nodes and signals as graph edges, each containing their respective names. - Generate a Verilog hierarchy from the graphic representation. There are two options: generate a Verilog stub containing just the module and signals declaration (to include this using a Verilog `include directive in a complete Verilog design file) or modify the declarations in an existing design file. Notes: - Target Verilog language is Verilog 2001. The parser is simple (Verilog modules and signals) so it could be written directly. Otherwise, ANTLR may be used. - The different styles of valid signal declarations must be supported. Eg, using reg's, named (dotted) and unnamed (ordered) ports, etc. - Previous experience in Verilog is a plus, but it is really not needed. The language features the application is focusing on could be learned in less than an hour. The important aspect is the development of a simple and intuitive graphical application.

## Deliverables

1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done.

2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables):

a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment.

b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request.

3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement).

## Platform

Windows NT/2000/XP/Vista.

Habilidades: PHP

Ver mais: verilog parser, verilog module graph, xml code generator, windows uml tool, window design group, web design generator, web design drag and drop, visual hierarchy in graphic design, visual hierarchy graphic design, uml tool for windows, uml tool, uml development tool, uml c# tool, uml application design, tree of a graph, tree graph, tree and graph, tool uml, styles for less application, styles for less, signal express, s&c electric, representation graph, php web development graph, php parse tree

Acerca do Empregador:
( 2 comentários ) United States

ID do Projeto: #2991261

4 freelancers estão ofertando em média $1930 para este trabalho

alexadesignvw

See private message.

$1428 USD in 30 dias
(7 Comentários)
4.8
thecloudkernel

See private message.

$1615 USD in 30 dias
(5 Comentários)
3.4
man0110

See private message.

$425 USD in 30 dias
(8 Comentários)
3.2
zanestarr

See private message.

$4250 USD in 30 dias
(0 Comentários)
0.0