Synthesis of Rectangle Processor Behavioral code: `define IDLE 2'b00 `define READY 2'b01 `define RUNNING 2'b10 module xy_counter (coord, done, startVal, endVal, run, load); output [4:0] coord; // coordinate output done; // 1 if coord == endVal input [4:0] startVal; // starting value input [4:0] endVal; // ending value input run; // 1 => run the counter input load; // loads startVal reg [1:0] state; // counter state reg [4:0] coord; // coordinate reg clock; // clock generator // Assigns the done output based on the count value. // Substitute an equality tester module here. // Add a mux and incrementer like the class example. assign done = (coord == endVal); initial begin state = `IDLE; coord = 0; clock = 0; end // Generate the clock signal always # 5 clock = ~ clock; // Inside this “always?? block, your synthesized code // should only assign “state = next_state?? and // “coord = next_coord??. The values of next_state and // next_coord should be generated by gates and // instantiated modules outside this block. always (posedge clock) begin case (state) `IDLE: begin if (load) begin coord = startVal; state = `READY; end else state = `IDLE; end `READY: if (run) state = `RUNNING; else if (done) state = `IDLE; else state = `READY; `RUNNING: begin coord = coord + 1; if (done) state = `IDLE; else if (!run) state = `READY; else state = `RUNNING; end default: begin $display("Illegal state in xy_counter!"); $finish; end endcase end endmodule
1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Installation package that will install the software (in ready-to-run condition) on the platform(s) specified in this bid request. 3) Exclusive and complete copyrights to all work purchased. (No GPL, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site). LOTS OF COMENTS DUE DATE: 11/30/2003 cont. Synthesize the counter module from Assignment 2 as described below. Then substitute the synthesized module for the behavioral version in your test module from Assignment 2. Test it with the rectangle coordinates from that assignment. The test module is the top-level module where the counter and controller modules of the processor are instantiated together. Note that you will have two instances of the same counter module in your test module, unless you used a different module for each counter. A copy of the behavioral code for the counter is included in this handout. You may synthesize the counter based on either the included code or the code you used for the counter in Assignment 2 (if your Assignment 2 output was correct). Some coordinates are repeated in the output of the code that is included here, so repeating coordinates will be acceptable in your synthesized version. You may use as many as you need of any of the valid Verilog gate types (and, or, xor, xnor and not). Each gate except “not?? can have any number of inputs (the “not?? gate can only have one, of course). You may also instantiate other modules inside the counter module to help you manage the structure of the design. However, the only behavioral structures in your synthesized counter should be: • The “initial?? block that sets starting values for registers (but do not use initial to set the counter to startVal ??" the load input should trigger this) • The “always?? block that generates the clock signal • An “always?? block to assign a next_state value to the state variable and a next_coord value to the coord register. For the coord register, you may use an “if?? to gate the clock with the load and increment signals. The next_state and next_coord values should be generated by gates and/or module instantiations (not behavioral structures). You do not need to add delays to any of the gates or module outputs. When you instantiate your synthesized counter into the test module, you should get the same output as when you used the behavioral version. This will tell you whether or not your synthesis was correct. Counter: A behavioral code listing for module xy_counter is given at the end of this section. You can synthesize this code by first breaking it up in the same way as was shown in the handout, “Synthesis Example ??" Counter??. The major components are: • finite state machine logic • load/increment logic • counter structure (equality tester, incrementer and mux) Generate a value for next_state using gates and assign the value to state within an “always (posedge clock)?? structure. The value of next_state is the value that is assigned to state under the conditions given in the case statement in the behavioral code. Also use gates to generate load and increment signals for the counter based on the case statement conditions. You may build the equality tester, incrementer and mux using the code samples given in “Gate/Module Delay Example ??" Counter??. You do not need to include the gate delays. Hints: • You can use the equality tester, incrementer and mux in virtually the same way as they were used in “Synthesis Example ??" Counter??. But instead of using a zero value to reload the coordinate register, you will need to use the starting value that you receive as an input.
WINDOWS XP • Use “not?? gates to generate inverted versions of the bits of the state variable and the input and output control signals. Then use both the inverted and non-inverted versions as needed to build your finite state machine and load/increment logic. • For the state machine logic, you can generate a control signal to represent each state based on the state variable. For example, to represent the RUNNING state: and and1 (running, state, not_state); where not_state is the inverse of state. Control signals like running can help you determine next_state in a more straightforward manner than drawing out truth tables and Karnaugh maps. • For each bit of next_state, consider which next states have the bit high. Then, examine the case statement to determine what values of state and control signals will cause one of those next states to be assigned to the state register. For example...