A testbench is a top-level module that applies a series of inputs to a design that you’re testing. The testbench reads the inputs for a given test from a file, allowing you to change the input values easily without modifying any Verilog code. The results of the test are written to an output file. For the rectangle processor, we will convert your top-level test module from Assignment 2 into a testbench by adding an input driver module and an output memory module. The input driver module will read the start and end coordinates for four rectangles from an input file and provide them in sequence to the X and Y counters. As the rectangle processor generates coordinates for a rectangle with its write signal high, a color value from the input file will be written to the output memory at each set of coordinates within the rectangle. At the same time, the output memory module will write the simulation time, coordinates, memory address and color value to the screen and an output file. The rules for writing a testbench are more relaxed than for writing the design being tested, because the testbench does not represent actual physical hardware. You may still need clocks to control certain registers in the input driver and output memory modules, and these clocks should run at the same rate as the clocks inside your processor. But you do not need to design a finite state machine to control any part of the testbench. The objective is simply to write code that controls the processor and captures output in the manner described here. PLEASE EMAIL ME FOR MORE DETAILS.
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