Em Andamento

Verilog Program - Part 2 of 4

RECTANGLE PROCESSOR: The rectangle processor generates coordinates and a write signal that can be used to draw filled rectangles in an external memory. This assignment will focus only on the design of the [url removed, login to view] rectangle processor generates coordinates and a write signal that can be used to draw filled rectangles in an external memory. This assignment will focus only on the design of the processor. The rectangle processor consists of a controller block and two identical five-bit counters. The controller receives a go signal from a register to tell it when to start drawing. It generates a write signal while it is drawing a rectangle, and an idle signal when the rectangle is finished. Each counter receives starting and ending values (startX, endX, startY, endY) that define the boundaries of the rectangle. The rectangle includes all the pixels that reside on all of the boundaries. The controller and the counters all run at the same clock rate. When the controller sees the go signal high, it sets both loadX and loadY high for one clock cycle. This loads the two counters with their starting values (startX and startY), setting Xcoord and Ycoord to the top left corner of the rectangle. The controller then allows counterX to run by setting runX high. The counter increments Xcoord by one at every positive clock edge. The doneX signal tells the controller when Xcoord reaches endX. At that point, the coordinates are at the end of the first line. The controller then sets runY high for one clock cycle to allow Ycoord to increment by one. At the same time, it sets loadX high again, reloading counterX with the startX value. The coordinates are then at the beginning of the second line. The controller sets runX high again until doneX goes high. Then Ycoord is incremented again and counterX is reloaded with startX to begin the next line. The process repeats until the coordinates reach (endX, endY). At that point, doneX and doneY are both high, prompting the controller to raise the idle signal. As mentioned above, counterX and counterY are identical modules. The state diagram for counterX is shown and described below. The diagram and description for counterY would be the same as for counterX, except that the variable names would change as follows: loadX becomes loadY startX becomes startY runX becomes runY endX becomes endY doneX becomes doneY Xcoord becomes Ycoord

## Deliverables

1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done.

2) Installation package that will install the software (in ready-to-run condition) on the platform(s) specified in this bid request.

3) Exclusive and complete copyrights to all work purchased. (No GPL, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site).

4)Instantiate the three modules of the processor together inside a test module, and test the processor with the values specified under Input values. 5) LOTS OF COMMENTS ================= The counter starts in the IDLE state. In that state, Xcoord remains unchanged until loadX goes high. Then, at the next positive clock edge, Xcoord must be set to startX as the state changes to READY. These two assignments can be done at the same point in the case statement for the state. If startX and endX are the same, then doneX goes high in the READY state, and the counter returns to IDLE on the next positive clock edge. The runX signal changes the state from READY to RUNNING. In the RUNNING state, Xcoord is incremented by one at every positive clock edge. The doneX signal goes high whenever Xcoord is equal to endX. If the runX signal drops low before doneX goes high, the state returns from RUNNING to READY, and the count stops incrementing until runX goes high again. If doneX goes high in the RUNNING state, then Xcoord has reached endX, and the counter returns to IDLE at the next positive clock edge. The controller block has four states, as shown below. The controller, like the counters, starts in the IDLE state. When the go signal is high, it changes to the LOAD state and loads the counters. Then it moves unconditionally to RUN_X, where the runX signal is set high. This causes counterX to increment from the left side of the rectangle to the right. In the case statement, the unconditional transition looks like: `LOAD: state = `RUN_X; When doneX goes high in the RUN_X state, Xcoord has reached the end of a line (endX). If it isn’t the last line of the rectangle, then doneY is low, and the state changes to NEXT_Y. At that point, Ycoord is incremented by one, and counterX is reloaded with startX. The X and Y coordinates are then at the beginning of the next line. The controller returns unconditionally to the RUN_X state and allows Xcoord to increment across the rectangle again. On the last line of the rectangle, Ycoord is equal to endY, so doneY is high. When doneX also goes high, the counters have reached the last pixel of the rectangle. The state then changes from RUN_X to IDLE, and the controller raises the idle [url removed, login to view] values of the outputs from the controller are defined as follows: runX is high only in the RUN_X state runY is high only in the NEXT_Y state loadX is high in both the LOAD and NEXT_Y states loadY is high only in the LOAD state idle is high only in the IDLE state write is high only in the RUN_X state Write the Verilog code for the controller. Then write a test module where you declare one instance of your controller and two instances of the given counter module. Connect these instances to complete the processor, and test the processor as shown below. Input values: Test your implementation with the following set of inputs: startX = 14 startY = 15 endX = 17 endY = 18 Program your input registers with this set of values and set your go register high. Wait at least one clock cycle, then set go low again and wait for idle to go high. You may then end the simulation with $finish. Hints: • The counter module code has generic signal names (e.g. load instead of loadX or loadY). You can use two identical instances of the counter module as counterX and counterY, respectively.

## Platform

WINDOWS XP • Declare wires and regs in the test module with names that are specific to counterX or counterY and connect them to the generic ports on the appropriate counter (e.g. connect loadX in the test module to the load input of counterX). The controller must have port names that are specific to each counter (e.g. a loadX output and a loadY output). • Make sure you only leave the go input high long enough to get the controller’s state machine out of IDLE state (that is, until idle drops low). Then, use a “wait?? specifier to wait for the idle signal to go high again before ending the simulation. • Use “assign?? statements to define the single-bit outputs of the controller (idle, write, etc.) based on the controller’s state.

Habilidades: Engenharia, Microsoft, MySQL, PHP, Arquitetura de software, Teste de Software, Área de trabalho do Windows

Ver mais: use of use case diagram, used case diagram, use case module, use case drawing software, use case drawing, use case diagram of, use case diagram for software design, use case diagram for, use case diagram components, three line drawing, three line diagram, the design cycle, rectangle line, program to draw use case diagram, process of package design, make a use case diagram, line rectangle, includes in use case, generic components, first 2 the finish, first 2 finish, drops design, draw use case diagram, draw use case, drawing use case diagram

Acerca do Empregador:
( 16 comentários ) United States

ID do Projeto: #2987133

Premiar a:


See private message.

$34 USD em 5 dias
(17 Avaliações)

2 freelancers estão ofertando em média $81 para este trabalho


See private message.

$127.5 USD in 5 dias
(18 Comentários)