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Verilog Program - Part 1 of 4

Problem 1: Write a structural model for a 5-bit equality tester. Specifications: • The equal output should be high whenever there are equal values on inputs in1 and in2. • Use regs only for driving the inputs. The design itself should be purely combinational. • Do not use the == operator to compare in1 and in2. This is to be a structural model using only gates and module instantiations! • Test your design using the following sets of inputs, shown as “decimal (binary)??: in1 in2 4 (00100) 27 (11011) 6 (00110) 24 (11000) 3 (00011) 31 (11111) 21 (10101) 13 (01101) 27 (11011) 11 (01011) 15 (01111) 15 (01111) Hints: • Compare each bit of in1 with the corresponding bit of in2 (that is, in1[0] with in2[0], in1[1] with in2[1], etc.). If every pair of bits is equal, the two inputs are equal. • In the above table, note that for the first pair of inputs (4 and 27), bits 0 through 4 all mismatch. The second pair (6 and 24) mismatches for all bits except bit 0, the third pair mismatches for all bits except bits 0 and 1, and so forth. You can check the individual bit comparisons to confirm that another bit pair is matching with each successive pair of inputs, until all bit pairs match at the last pair of inputs. Problem 2: Write a structural model for a 5-bit 2-to-1 multiplexer. Specifications: • When sel = 0, out = in1. When sel = 1, out = in2. • Use regs only for driving the inputs. The design itself should be purely combinational. • Do not use an if-else structure or the conditional operator (“?:??) to select between in1 and in2. This is to be a structural model using only gates and module instantiations! • Test your design using the following sets of inputs: in1 in2 sel 4 (00100) 27 (11011) 0 6 (00110) 24 (11000) 1 3 (00011) 31 (11111) 0 21(10101) 13 (01101) 1 27(11011) 11 (01011) 0 Hints: • Use predefined gates to build a module containing a one-bit 2-to-1 multiplexer. • You may use the 2-to-1 multiplexer design presented in class (but add ports!) • Instantiate the one-bit multiplexer 5 times inside another module. • Connect the 5 multiplexers in parallel, using the same sel signal for all of them. • The values for in1 and in2 are the same as for Problem 1, except that the last case from Problem 1 is omitted here. If your results are not correct, use the differing bit in each case to see if the proper input is being selected.

## Deliverables

1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Installation package that will install the software (in ready-to-run condition) on the platform(s) specified in this bid request. 3) Complete ownership and distribution copyrights to all work purchased. 4) Lots of comments For each of the problems described: Use statements such as $display and $monitor in your code to show both your inputs and the resulting outputs. You may also include internal signals in your output if you wish (optional).Submit all the Verilog code that you write. You may create a WinZip file for the entire assignment. cont. Problem 3: Write a structural model for a 5-bit adder. Specifications: • out = in1 + in2 • Use regs only for driving the inputs. The design itself should be purely combinational. • Do not use the + operator to add in1 and in2. This is to be a structural model using only gates and module instantiations! • Test your design using the following sets of inputs: in1 in2 5 9 11 18 21 6 8 15 27 23 Hints: • Use predefined gates to build a module containing a one-bit adder without carry-in and a one-bit adder with carry-in. • You may use the full adder designs presented in class (but add ports!) • Instantiate the full adder without carry-in once inside another module. This will be the adder for the least significant bits of in1 and in2. • Instantiate the full adder with carry-in 4 times inside the same module where you instantiated the adder without carry-in. These four instances will handle the highest 4 bits of the inputs. • Connect each carry-out to the carry-in of the next higher adder. • Output bit out[5] is the carry-out of the highest adder. • Each pair of inputs in the table above generates a carry-out from only one of the adders, except the last case, which generates carry-outs from all the adders. If your results are not correct, check to see that the carry-out is being generated as expected and is being counted in the next higher adder.

## Platform

windows

Habilidades: Engenharia, Microsoft, MySQL, PHP, Arquitetura de software, Teste de Software, Área de trabalho do Windows

Ver mais: use of binary, use case module, structural design work, problems with match, problem statements, part problem, no problem part 1, match problems, conditional design, c code for assignment problem, bits of, bit bits, bit binary, binary problems, binary problem, binary code test, binary bit, assignment problems in or, assignment out source, all the bits, all bits, 1 bits, h4 working, h4 work, h4 can work

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