# verilog program

Problem 1: Write a structural model for a 5-bit equality tester. Specifications: • The equal output should be high whenever there are equal values on inputs in1 and in2. • Use regs only for driving the inputs. The design itself should be purely combinational. • Do not use the == operator to compare in1 and in2. This is to be a structural model using only gates and module instantiations! • Test your design using the following sets of inputs, shown as “decimal (binary)??: in1 in2 4(00100) 27(11011) 6(00110) 24(11000) 3(00011) 31(11111) 21(10101) 13(01101) 27(11011) 11(01011) 15(01111) 15(01111) Hints: • Compare each bit of in1 with the corresponding bit of in2 (that is, in1[0] with in2[0], in1[1] with in2[1], etc.). If every pair of bits is equal, the two inputs equal. • In the above table, note that for the first pair of inputs (4 and 27), bits 0 through all mismatch. The second pair (6 and 24) mismatches for all bits except bit third pair mismatches for all bits except bits 0 and 1, and so forth. You can the individual bit comparisons to confirm that another bit pair is matching with each successive pair of inputs, until all bit pairs match at the last pair of inputs. Problem 2: Write a structural model for a 5-bit 2-to-1 multiplexer. Specifications: • When sel = 0, out = in1. When sel = 1, out = in2. • Use regs only for driving the inputs. The design itself should be purely combinational. • Do not use an if-else structure or the conditional operator (“?:??) to select between in1 and in2. This is to be a structural model using only gates and module instantiations! • Test your design using the following sets of inputs: in1 in2 sel 4(00100) 27(11011) 0 6(00110) 24(11000) 1 3(00011) 31(11111) 0 21(10101) 13(01101) 1 27(11011) 11(01011) 0 Hints: • Use predefined gates to build a module containing a one-bit 2-to-1 multiplexer. • You may use the 2-to-1 multiplexer design presented in class (but add ports!) • Instantiate the one-bit multiplexer 5 times inside another module. • Connect the 5 multiplexers in parallel, using the same sel signal for all of them. • The values for in1 and in2 are the same as for Problem 1, except that the last case from Problem 1 is omitted here. If your results are not correct, use the differing bit in each case to see if the proper input is being selected. Problem 3: Write a structural model for a 5-bit adder. Specifications:• out = in1 + in2

## Deliverables

## Platform

windows reg in1, in2; // inputs wire sum, c_out; // sum and carry-out // Instantiate gates ??" generate sum and carry-out xor sum1and2 (sum, in1, in2); and carry_out (c_out, in1, in2); initial begin // Set the inputs in1 = 1'b1; in2 = 1'b0; // Wait 1 time unit, then print the inputs #1 \$display("in1 = %b",in1); \$display("in2 = %b",in2); // Print the results \$display("sum = %b",sum); \$display("c_out = %b",c_out); end endmodule send the rest later (did not have enough space)