This assignment is to simulate cache memory architecture, operations and performance.
You will have to write a cache memory simulator with the following assumptions and specifications.
1. Basic functions of the simulator to be implemented (80 points)
Enter the size of memory reference in bits (e.g., 8, 16, 32 bits):
Enter the size of the cache in MB (e.g., 1, 128, 256, 512):
Enter the cache block size in bytes per block:
Enter the cache set associativity:
Enter the cache replacement algorithm (LRU or random):
Assume that the cache is initially empty. Note that all those sizes above are correlated.
Generate memory reference sequence and assume a random number generator with locality of reference to be considered. Specify what random number generator you used with a citation.
Determine the length of memory reference (e.g., 100, 1000, 10000):
Start executing your simulator with the memory reference list generated above.
Print the current memory reference in binary bit string:
Print for the current memory reference the TAG field, the set offset field, the byte offset field in decimal:
Print for the current memory reference whether it’s a hit or a miss in the following format, “TAG, LRU bit, Hit bit” (LRU bit is set to 1 if the current block of reference is least recently used one; Hit bit is set to 1 if the current reference is a hit):
2. Performance analysis (80 points)
Using your simulator, perform an extensive simulation to study the miss rate trend of the cache versus the size of the cache, the cache block size, the cache set associativity, the cache replacement algorithm. Then,
Enter the size of memory reference string in bits:
Enter the range of the size of the cache in MB:
Enter the range of the size of the block in MB:
Enter the cache set associativity:
Enter the cache replacement algorithm of choice (“L” for LRU, “R” for random):
Enter the memory reference length (e.g., 10, 100, 1000):
Run the simulator with the above memory references!
1. A plot of Miss rate (0.0 – 1.0 on y-axis) versus the size of the cache (x-axis) for each cache replacement algorithm and each set associativity. You may plot in 3D or multiple plots on a 2D graph for better readability. And an equivalent Table should be printed as an output to the simulation.
2. A plot of Miss rate (0.0 – 1.0 on y-axis) versus the size of the block (x-axis) for each cache size in multiple plots on a 2D graph. And an equivalent Table should be printed as an output to the simulation.
3. A plot of Miss rate (0.0 – 1.0 on y-axis) versus the set associativity of choice (x-axis) for each cache size in multiple histograms. And an equivalent Table should be printed as an output to the simulation.
Write and submit a report on the performance analysis you conducted in 3 pages, 1 page for each output.
3. Performance optimization (140 points)
Incorporate multi-level cache into the simulator you developed in 1) and 2).
Enter the levels of the cache (e.g., 1, 2 or 3):
Enter the spatial ratio of adjacent cache levels (e.g., 10%, 15, 30%, maintain the total cache size intact as it breaks into multilevel cache):
Repeat the simulation in steps 1) and 2) with the extra input as entered in 3).
There will be extra plots for different cache levels and spatial ratio.
4 freelancers are bidding on average $33 for this job
Hi, I am a MSc. COmputer Science final year with experience of computer architectures and embedded systems(microcontrollers). I am ready to create your cache simulation. Thanks