Details: The purpose of this project is to help solidify your understanding of the details of how caches and memory work by building a multi-level cache and memory model that processes address traces concurrently on a dual-core CPU. Your caches must support several design options and be configurable. For example, your cache simulator should support different sizes (number of entries), different cache line sizes, and different levels of associativity as described in the following sections. You will need to maintain hit/miss ratio statistics as well as a running average of instruction latencies during execution that will be aggregated into reportable performance metrics upon completion of address trace processing.
Details are attached. I have chapter notes also.