4. Project Description:
The goal is the design of a 4-bit adder. Inputs are two 4-bit numbers A & B. Output is 4-
bit sum and a carry.
5. Step-by-Step Description:
- Start with the design of a minimum sized inverter, i.e., Lp = Ln = Lmin = 250 nm, and Wp
= Wn = Wmin = 350 nm. Simulate the circuit schematic. From the voltage transfer
characteristic, identify the switching voltage VM and the noise margins.
- Gradually increase the width of the PMOS transistor as multiple of Wn, i.e., use Wp =
2Wn, Wp = 3 Wn, …. etc until you reach a matched inverter. Verify that the inverter is
indeed matched by showing that VM ≈ VDD/2.
- The size of the PMOS transistor in the matched inverter will be used to specify the size
of all transistors in the CMOS logic gates of the full-adder.
- The full-adder circuit explained in class involves the following logical circuits:
- Construct each of these CMOS logic circuits and size the transistors with accordance to
the matched inverter.
- Verify the correct functionality of each circuit through schematic level simulation.
- Construct each circuit on the layout level in L-Edit and verify correct functionality by
performing post-layout simulation.
- The layout of each circuit should be free of DRC except for density errors.
- Combine all the circuits designed and tested in step two to implement a full-adder.
- Verify correct functionality of the full-adder through schematic and post layout
- Combine the four full-adders to construct a 4-bit adder.
- Verify the functionality of the 4-bit adder though schematic and post layout simulations.
6. Performance Measure:
- Choose an optimum test vector to test your design
14 freelancers estão ofertando em média $202 para este trabalho
i completed [url removed, login to view] vlsi . i can do it for u... my thesis is related to this multipliers so i used adders in my thesis also...ece is my back ground
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