Implementing FPGA Handshaking System

Implementing FPGA Handshaking System Objectives

This project will be an individual project. You need to use Altera Quartus II to finish the handshaking protocol code using Verilog HDL.

This project will allow students to learn how to design state machine using Verilog HDL for FPGA system and to understand the handshaking protocol that is used in various systems to transmit the data. Assignment

In this assignment, you will learn how to develop a FPGA system using Altera Quartus II EDA software, and how to use ModelSim simulation system to verify your design. For this assignment, you should submit a paper to show your design, including the code with all necessary detailed tables, wave diagram(s), and descriptions. Descriptions Please read the [url removed, login to view] file, and download the source code. Prepare a Statechart Diagram. You need to write all detailed information in this diagram, such as triggers (events), list of actions (actions with event, or entry/do/exit actions in state), and any guards. Write a detailed description about your Statechart Diagram, as in your second homework assignment. According to your Statechart Diagram, complete the HS_Protocol.v code.

Execute the ModelSim and capture the waveform for the hs_protocol module. The following signals should be included: CLK USB_WR, USB_RD, USB_RDYREQ, USB_ACK, USB_DONE, USB EMPTY CurrentState CODE_WR, CODE_RD, CODE_RDYREQ, CODE_ACK, CODE_EMPTY Identify the rising/falling edges in your handshaking protocol on your waveform. Include your completed source code for HS_Protocol.v as an appendix to your report.

Habilidades: Modelagem 3D

Veja mais: students data entry software, learn verilog, learn how to design, how to write report pdf, how to write a report on an event, how to write a report for homework, how to learn how to code, do your homework for you, absas, system verilog, machine learn, learn to write code, hdl code, eda, altera, file system simulation, implementing project, simulation paper, verilog write, state diagram, fpga design verilog, implementing assignment, design protocol assignment, fpga code, FPGA design

Acerca do Empregador:
( 88 comentários ) Delhi, India

ID do Projeto: #6833126

2 freelancers estão ofertando em média $28 para esse trabalho


hi , i have been working as 3d designer for more than 15 years and i can create any object you need with good quality , you can also check my portfolio . Thanks with best regards Pouya

$30 USD em 1 dia
(2 Comentários)

A proposal has not yet been provided

$25 USD em 1 dia
(0 Comentários)