I want to design a verilog module where input is AXI Stream and output can be either RAW10 or RAW12 pixel data as per input selection. I have my own code for MIPI RAW8. Need to add RAW10 and RAW12 functionality.
2 freelancers estão ofertando em média ₹925 para esse trabalho
I have done many projects on functional verification, like AXI protocol verification, APB protocol verification, AHB master and slave UVC verification etc.