Debug my asynchronous circuit VHDL code

Project Description:


I'm making an asynchronous pipeline which mean every stage of pipeline control by local controller, using Quartus 2, written in VHDL language. The problem i'm facing is unversity waveform program shown that the data is not transferred between stages as shown in below images. The function of the pipeline is converting integer into 2nd complement.. The pipeline has three stages.

There are two states to decide either want to transfer the data between stages or no.

State0 - transfer data between stages when successor is full and predecessor is empty

State1 - disable data transfer between stages when successor is empty and predecessor is full.

This is will be very easy for you since you are an expert . I did post my problem into [url removed, login to view] and someone did manage to simulate it, but when I try I cant.. I hope you able to fix this

Tool : Altera Quartus 2 and VHDL

Expectation from you: Able to simulate functional and timing simulation successfully.

I will attach you the code if you agree.

Habilidades: FPGA, Verilog / VHDL

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( 1 comentário ) Kuala Lumpur, Malaysia

ID do Projeto: #6831374

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